AD7008

Features:

Single +5 V Supply
32-Bit Phase Accumulator
On-Chip COSINE and SINE Look-Up Tables
On-Chip 10-Bit DAC
Frequency, Phase and Amplitude Modulation
Parallel and Serial Loading
Software and Hardware Power Down Options
20 MHz and 50 MHz Speed Grades
44-Pin PLCC


Application

Frequency Synthesizers
Frequency, Phase or Amplitude Modulators
DDS Tuning
Digital Modulation


Pinout




Specifications

V_AA, V_DD to GND  . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +7 V
AGND to DGND  . . . . . . . . . . . . . . . . . . . . .     0.3 V to +0.3 V
Digital I/O Voltage to DGND  . . . . . . . .  0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND  . . . . . . . . 0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A Version)  . . . . . . . . . . . . . . . . .  40°C to +85°C
Commercial (J Version)  . . . . . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature Range  . . . . . . . . . . .65°C to +150°C
Lead Temperature (Soldering, 10 secs)  . . . . . . . . . . +300°C
Junction Temperature  . . . . . . . . . . . . . . . . . . . . . . .  +115°C
PLCC _JA Thermal Impedance  . . . . . . . . . . . . . . .+53.8°C/W
           _JC Thermal Impedance  . . . . . . . . . . . . .  +24.1°C/W


Description

The AD7008 direct digital synthesis chip is a numerically controlled oscillator employing a 32-bit phase accumulator, sine and cosine look-up tables and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation, frequency modulation, and both in-phase and quadrature amplitude modulation suitable for QAM and SSB generation. Clock rates up to 20 MHz and 50 MHz are supported. Fre- quency accuracy can be controlled to one part in 4 billion. Modulation may be effected by loading registers either through the parallel microprocessor interface or the serial interface. A frequency-select pin permits selection between two frequencies on a per cycle basis.

The serial and parallel interfaces may be operated independently and asynchronously from the DDS clock; the transfer control signals are internally synchronized to prevent metastability problems. The synchronizer can be bypassed to reduce the transfer latency in the event that the microprocessor clock is synchronous with the DDS clock. A power-down pin allows external control of a power-down mode (also accessible through the microprocessor interface)
The AD7008 is available in 44-pin PLCC.