Features: Guaranteed 16-Bit MonotonicityMonolithic BiMOS II Construction60.01% Typical Nonlinearity8- and 16-Bit Bus Compatibility3 ms Settling to 16 Bits Low Drift Low Power Low NoiseApplicationRoboticsClosed-Loop PositioningHigh-Resolution ADCsMicroprocessor-Based Process ControlMIL-STD-883 Compliant Versions AvailablePinout
Specifications(TA = +25°C unless otherwise noted)
+VS (Pin 1) to GND (Pin 18) . . . . . . . . . . . . . . +18 V, 0.3 V
VS (Pin 28) to GND (Pin 18) . . . . . . . . . . . . . . 18 V, +0.3 V
+VS (Pin 1) to VS (Pin 28) . . . . . . . . . . . . . . . +26.4 V, 0.3 V
Digital Inputs
(Pins 4-14, 19-27) to GND (Pin 18) . . . . . . . . . . . .. . .+VS, 0.3 V
+VREF Force (Pin 3) to +VREF Sense (Pin 2) . . . . . . . . . . ±16.5 V
VREF Force (Pin 15) to VREF Sense (Pin 16) . . . . . . . ±16.5 V
VREF Force (Pins 3, 15) to GND (Pin 18) . . . . . . . . . . . .. . . . ±VS
VREF Sense (Pins 2, 16) to GND (Pin 18) . . . . . . . . . . .. . . . . ±VS
VOUT (Pin 17) . . . . . . . . . . . . . . . . . .. . .. Indefinite Short to GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to +VS, VS
Power Dissipation (Any Package) . . . . . . . . . . . . . . . 1000 mW
Operating Temperature Range
Commercial Plastic (JN, KN, JP, KP Versions) 0°C to +70°C
Industrial Ceramic (AD, BD Versions) . . . . . . .. . 25°C to +85°C
Extended Ceramic (SD Versions) . . . . . . . . . .. 55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Lead Temperature Range (Soldering, 10 secs) . . . . . . . +300°CDescriptionThe AD569 is a monolithic 16-bit digital-to-analog converter(DAC) manufactured in Analog Devices' BiMOS II process.BiMOS II allows the fabrication of low power CMOS logicfunctions on the same chip as high precision bipolar linear circuitry.The AD569 chip includes two resistor strings, selectorswitches decoding logic, buffer amplifiers, and double-bufferedinput latches.
The AD569's voltage-segmented architecture insures 16-bitmonotonicity over time and temperature. Integral nonlinearity ismaintained at ±0.01%, while differential nonlinearity is±0.0004%. The on-chip, high-speed buffer amplifiers provide avoltage output settling time of 3 ms to within ±0.001% for afull-scale step.
The reference input voltage which determines the output rangecan be either unipolar or bipolar. Nominal reference range is±5 V and separate reference force and sense connections areprovided for high accuracy applications. The AD569 can operatewith an ac reference in multiplying applications.
Data may be loaded into the AD569's input latches from 8- and16-bit buses. The double-buffered structure simplifies 8-bit businterfacing and allows multiple DACs to be loaded asynchronouslyand updated simultaneously. Four TTL/LSTTL/5 VCMOS-compatible signals control the latches: CS, LBE,, HBE,and LDAC
The AD569 is available in five grades: J and K versions arespecified from 0°C to +70°C and are packaged in a 28-pin plasticDIP and 28-pin PLCC package; AD and BD versions arespecified from 25°C to +85°C and are packaged in a 28-pinceramic DIP. The SD version, also in a 28-pin ceramic DIP, isspecified from 55°C to +125°C.
AD569 Data Sheet
