AD568

V_CC to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
V_EE to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 18 V
REFCOM to LCOM . . . . . . . . . . . . . . . . . +100 mV to 10 V
ACOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mV
THCOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 mV
SPANs to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±12 V
IBPO to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V
IOUT to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to V_TH
Digital Inputs to THCOM . . . . . . . . . . . . . 500 mV to +7.0 V
Voltage Across Span Resistor . . . . . . . . . . . . . . . . . . . . . . 12 V
VTH to THCOM . . . . . . . . . . . . . . . . . . . . . . 0.7 V to +1.4 V
Logic Threshold Control Input Current . . . . . . . . . . . . . 5 mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mW
Storage Temperature Range
Q (Cerdip) Package . . . . . . . . . . . . . . . . . 65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Thermal Resistance
qA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
qC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C/W

The AD568 is an ultrahigh-speed, 12-bit digital-to-analog converter(DAC) settling to 0.025% in 35 ns. The monolithic deviceis fabricated using Analog Devices' Complementary Bipolar(CB) Process. This is a proprietary process featuring high-speedNPN and PNP devices on the same chip without the use ofdielectricisolation or multichip hybrid techniques. The high speedof the AD568 is maintained by keeping impedance levels lowenough to minimize the effects of parasitic circuit capacitances.

The DAC consists of 16 current sources configured to deliver a10.24 mA full-scale current. Multiple matched current sourcesand thin-film ladder techniques are combined to produce bitweighting. The DAC's output is a 10.24 mA full scale (FS) forcurrent output applications or a 1.024 V FS unbuffered voltageutput. Additionally, a 10.24 V FS buffered output may be generatedusing an onboard 1 kW span resistor with an external opamp. Bipolar ranges are accomplished by pin strapping.

Laser wafer trimming insures full 12-bit linearity. All grades ofthe AD568 are guaranteed monotonic over their full operatingtemperature range. Furthermore, the output resistance of theDAC is trimmed to 100 ± 1.0%. The gain temperaturecoefficientof the voltage output is 30 ppm/ max (K).

The AD568 is available in three performance grades. TheAD568JQ and KQ are available in 24-pin cerdip (0.3") packagesand are specified for operation from 0 to +70. TheAD568SQ features operation from 55°C to +125 and is alsopackaged in the hermetic 0.3" cerdip.