Features: Guaranteed monotonic
INL error: ±1 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/ reference
Temperature range: 40 to +85
Rail-to-rail output amplifier
Power-down
Package type: 100-lead LQFP (14 mm * 14 mm)
User Interfaces:
Parallel
Serial (SPI®/QSPI™/MICROWIRE™/DSP compatible,
featuring data readback)
I2C® compatibleApplicationVariable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMs)
Control systems
InstrumentationPinout
Specifications
| Resolution (Bits) |
12bit |
| DAC Update Rate |
167kSPS |
| DAC Settling Time |
6s |
| # DAC Outputs |
40 |
| DAC Type |
Voltage Out |
| DAC Input Format |
Par,Ser,SPI |
| Output FSR |
(Uni 2.5V),(Uni 2Vref),(Uni 5V),User Def. Range/Offset |
| Ref Int/Ext |
Int/Ext |
| Supply Vnom |
Single(+3),Single(+3.3),Single(+5) |
| Package |
QFP |
Table 9. TA = 25, unless otherwise noted1
| Parameter |
Rating |
| AVDD to AGND |
0.3 V to +7 V |
| DVDD to DGND |
0.3 V to +7 V |
| Digital Inputs to DGND |
0.3 V to DVDD + 0.3 V |
| SDA/SCL to DGND |
0.3 V to + 7 V |
| Digital Outputs to DGND |
0.3 V to DVDD + 0.3 V |
| REFIN/REFOUT to AGND |
0.3 V to DVDD + 0.3 V |
| AGND to DGND |
0.3 V to +0.3 V |
| VOUTx to AGND |
0.3 V to AVDD + 0.3 V |
| Analog Inputs to AGND |
0.3 V to AVDD + 0.3 V |
| Operating Temperature Range |
|
| Commercial (B Version) |
40 to +85 |
| Storage Temperature Range |
65 to +150 |
| JunctionTemperature (TJ Max) |
150 |
| 100-lead LQFP Package |
|
| JAThermal Impedance |
44/W |
| Reflow Soldering |
|
| Peak Temperature |
230C |
DescriptionThe AD5381 is a 40-channel, 12-Bit DAC and is available in a 14 mm x 14 mm 100-lead LQFP package. It operates from a single 3 V or 5 V supply. Programmable gain (m) and offset (c) are provided per
The AD5381 is a complete, single-supply, 40-channel, 12-bit DAC available in a 100-lead LQFP package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5381 includes a programmable internal 1.25 V/2.5 V, 10 ppm/°C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode that allows optimization of the amplifier slew rate. The AD5381 contains a double-buffered parallel interface that features a 20 ns WR pulse width, an SPI/QSPI/MICROWIRE/DSP compatible serial interface with interface speeds in excess of 30 MHz, and an I2C compatible interface that supports a 400 kHz data transfer rate.
An input register followed by a DAC register provides double buffering, allowing the DAC outputs to be updated indepen-dently or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust register that allows the user to fully calibrate any DAC channel. Power consumption is typically 0.25 mA/channel with boost mode disabled.
AD5381 Data Sheet
