AD5373

The AD5372 and AD5373 contain 32, 16-bit or 14-bit DACs in a single, 56-lead, LFCSP or 64-lead LQFP package. The AD5372/AD5373 provides buffered voltage outputs with a span 4 times the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into 4 groups of 8 DACs. Two offset DACs allow the output range of the groups to be altered.

The ADAD5372/AD5373 offers guaranteed operation over a wide supply range with VSS from -4.5 V to -16.5 V and VDD from+8 V to +16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.

The ADAD5372/AD5373 has a high-speed serial interface, which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.

The DAC outputs are updated on reception of new data into the DAC registers. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register.

Each DAC output is gained and buffered on-chip with respect to an external SIGGND input. The DAC outputs can also be switched to SIGGND via theCLR pin.