Features: AD5334: Quad 8-Bit DAC in 24-Lead TSSOPAD5335: Quad 10-Bit DAC in 24-Lead TSSOPAD5336: Quad 10-Bit DAC in 28-Lead TSSOPAD5344: Quad 12-Bit DAC in 28-Lead TSSOPLow Power Operation: 500 A @ 3 V, 600 A @ 5 VPower-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin2.5 V to 5.5 V Power SupplyDouble-...
AD5335: Features: AD5334: Quad 8-Bit DAC in 24-Lead TSSOPAD5335: Quad 10-Bit DAC in 24-Lead TSSOPAD5336: Quad 10-Bit DAC in 28-Lead TSSOPAD5344: Quad 12-Bit DAC in 28-Lead TSSOPLow Power Operation: 500 A @ ...
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(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . .0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . .0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . 0.3 V to VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . 40°C to +105°C
Storage Temperature Range . . . . . . . . . . 65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . (TJ max TA)/JA mW
JA Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
JA Thermal Impedance (28-Lead TSSOP) . . . . . 97.9°C/W
JC Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
JC Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W
Reflow Soldering
Peak Temperature . . . . . . .. . . . . . . . . . . . . .220 +5/0°C
Time at Peak Temperature . . . . . . . . . . . . .10 sec to 40 sec
The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and 12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 500 A at 3 V, and feature a power-down mode that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can drive the output to both supply rails.
The AD5334/AD5335/AD5336/AD5344 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR.
The GAIN pin on the AD5334 and AD5336 allows the output range to be set at 0 V to VREF or 0 V to 2 * VREF.
Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin.
On the AD5334, AD5335 and AD5336 an asynchronous CLR input is also provided. This resets the contents of the Input Register and the DAC Register to all zeros. These devices also incorporate a power-on-reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device.
The AD5334/AD5335/AD5336/AD5344 are available in Thin Shrink Small Outline Packages (TSSOP).