Features: Complete EIAJ CP-340 (CP-1201), IEC-958, AES/EBU,S/PDIF Compatible Digital Audio Receiver andAsynchronous Sample Rate Converter
Status Pins and Microprocessor Interfaces for Stand-Alone and Microcontroller-Oriented Operation
Integrated Channel Status Buffer and Q-Channel Subcode Buffer (Supports EIAJ CP-2401)
20-Bit SamplePort® Architecture Provides Superb Jitter Rejection on Input Port
Sample Rate Conversion from 8 kHz to 48 kHz with
-1:5 Upsampling Range
-1:0.85 Downsampling Range
-120 dB Dynamic Range
-113 dB THD+N @ 1 kHz
CRC Calculation on Q-Channel Subcode (Consumer Mode Only) and on Channel Status (Pro Mode Only)
Four-Wire SPI™ Compatible Serial Control Port
Mute Input Pin
Power-Down Mode
Single +5 V Supply
Flexible Three-Wire Serial Data Port with Left-Justified,Right-Justified and I2S-Compatible Modes
28-Lead SOIC Package
ApplicationDVD, DAT, MD, DCC and CD-R Recorders and Players
Computer Multimedia Products
DAB Receivers, Automotive Digital Audio NetworksPinout
Specifications
|
Min |
Max |
Units |
| VDD to GND |
0.3 |
7.0 |
V |
| DC Input Voltage |
0.3 |
DVDD + 0.3 |
V |
| Soldering |
|
+300 |
°C |
|
|
10 |
sec |
| DNR w/ Filter (+dB) |
120dB |
| THD+N @ 1kHz Input (-dB) |
113dB |
| Ratios |
1:0.85, 1:5 |
| Product Description |
Integrated Digital Receiver/Rate Converter |
DescriptionThe AD1892 combines a CP-1201, CP-340, IEC-958, AES/EBU, S/PDIF compatible Digital Audio Receiver (DAR) with an asynchronous sample rate converter, allowing the user to specify the output sample rate of the received digital audio information.The DAR block features support for both Q-channel subcode information (to support CD, CD-R, MD and DAT digital audio formats) as well as Channel Status information. A microcontroller interface, with an SPI compatible serial port,allows full access to the 80-bit Q-Channel subcode buffer and to the 32-bit Channel Status buffer, as well as to the control and status registers. Additionally, key status information from the incoming subframes and the Channel Status buffer is reported on status output pins on the AD1892, so the AD1892 may be used in systems that do not include a microcontroller or microprocessor.
The asynchronous sample rate converter block is based on market leading AD1890 family SamplePort rate conversion technology. The AD1892 offers a 1:5 upsampling range, and will downsample from 48 kHz to 44.1 kHz. Input audio word widths up to 20 bits are supported, and output audio word widths of 16 or 20 are supported, with 120 dB of dynamic range and 113 dB THD+N. The rate converter inherently rejects jitter on the recovered clocks from the incoming biphase-mark encoded stream. Indeed, sample rate conversion is highly synergistic with digital audio reception, allowing the use of a fully digital phase locked loop clock recovery scheme with highly robust clock recovery and jitter rejection.
AD1892 Data Sheet
