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ACT5270

Features: Full militarized QED RM5270 microprocessorDual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle 133, 150, 200 MHz operating frequencies Consult Factory for latest speeds 260 Dhrystone2.1 MIPS SPECInt95 5.0, SPECfp95 5.3High performanc...

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SeekIC No. : 004268013 Detail

ACT5270: Features: Full militarized QED RM5270 microprocessorDual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle 133, 150, 200 MHz operating frequencies...

ACT5270 Data Sheet

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Part Number:
ACT5270
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/22

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Product Details

Description



Features:

Full militarized QED RM5270 microprocessor
Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle
     133, 150, 200 MHz operating frequencies Consult Factory for latest speeds
     260 Dhrystone2.1 MIPS
     SPECInt95 5.0, SPECfp95 5.3
High performance system interface compatible with RM52 R4600, R4700 and R5000
     64-bit multiplexed system address/data bus for optimum price performance with up to 100 MHz operating frequency
     High performance write protocols maximize uncached write bandwidth
     Supports clock divisors (2, 3, 4, 5, 6, 7, 8)
     5V compatible I/O's
     IEEE 1149.1 JTAG boundary scan
Integrated on-chip caches
     16KB instruction - 2 way set associative
     16KB data - 2 way set associative
     Virtually indexed, physically tagged
     Write-back and write-through on per page basis
     Pipeline restart on first double for data cache misses
Integrated memory management unit
     Fully associative joint TLB (shared by I and D translations)
    48 dual entries map 96 pages
     Variable page size (4KB to 16MB in 4x increments)
Integrated secondary cache controller (R5000 compatible)
     Supports 512K or 2MByte block write-through secondary
High-performance floating point unit
     Single cycle repeat rate for common single precision operations and some double precision operations
     Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations
     Single cycle repeat rate for single precision combined multiply-add operation
MIPS IV instruction set
     Floating point multiply-add instruction increases performance in signal processing and graphics applications
     Conditional moves to reduce branch frequency
     Index address modes (register + register)
Embedded application enhancements
     Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction
     I and D cache locking by set
     Optional dedicated exception vector for interrupts
Fully static CMOS design with power down logic
      Standby reduced power mode with WAIT instruction
      6 Watts typical at 3.3V 200 MHz
208-lead CQFP, cavity-up package (F17)
208-lead CQFP, inverted footprint (F24), Intended to duplicate the commercial QED footprint
179-pin PGA package (Future Product) (P10)


Description

The ACT5270 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit,an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 64-bit system interface with support for an optional external secondary cache.The ACT5270 can issue both an integer and a floating point instruction in the same cycle.

The ACT5270 is ideally suited for high-end emb edded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization.The ACT5270 is also applicable to the low end workstation market where its balanced integer and floating-point performance and direct support for a large secondary cache (up to 2MB) provide outstanding price/performance

 


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