ACT5260

·  Full militarized QED RM5260 microprocessor
· Dual Issue superscalar QED RISCMark^TM - can issue one integer and one floating-point instruction per cycle   microprocessor - can issue one integer and one floating-point instruction per cycle
-100, 133 and 150MHz frequency (200MHz future option) Consult Factory for latest speeds
-260 Dhrystone2.1 MIPS
- SPECInt95 4.8. SPECfp95 5.1
· High performance system interface compatible with R4600,R4700 and R5000 -64-bit multiplexed system address/data bus for optimum price/performance up to 100 MHz operating frequency
-High performance write protocols maximize uncached write bandwidth
-Operates at input system clock multipliers of 2 through 8
-5V tolerant I/O's
-IEEE 1149.1 JTAG boundary scan
·Integrated on-chip caches - up to 3.2GBps internal data rate
-16KB instruction - 2 way set associative
-16KB data - 2 way set associative
-Virtually indexed, physically tagged
-Write-back and write-through on per page basis
-Pipeline restart on first double for data cache misses
· Integrated memory management unit
-Fully associative joint TLB (shared by I and D translations)
-48 dual entries map 96 pages
-Variable page size (4KB to 16MB in 4x increments)
· Embedded supply de-coupling capacitors and Pll filter components
· High-performance floating point unit - up to 400 MFLOPS
-Single cycle repeat rate for common single precision operations and some double precision operations
-Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations
-Single cycle repeat rate for single precision combined multiply-add operation
· MIPS IV instruction set
-Floating point multiply-add instruction increases performance in signal processing and graphics applications
-Conditional moves to reduce branch frequency
-Index address modes (register + register)
· Embedded application enhancements
-Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction
-I and D cache locking by set
-Optional dedicated exception vector for interrupts
· Fully static CMOS design with power down logic
- Standby reduced power mode with WAIT instruction
- 5 Watts typical at 3.3V, less than 175 mwatts in Standby
· 208-lead CQFP, cavity-up package (F17)
· 208-lead CQFP, inverted footprint (F24), Intended to duplicate the commercial QED footprint (Consult Factory)
· 179-pin PGA package (Future Product) (P10)

Notes:
1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. V_IN minimum = -2.0V for pulse width less than 15nS. VIN maximum should not exceed +5.5 Volts.
3. When V_IN < 0V or V_IN > Vcc.
4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second.

The ACT5260 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit,an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 64-bit system interface. The ACT5260 can issue both an integer and a floating point instruction in the same cycle.

The ACT5260 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization.