Features: ` Full militarized QED RM5230 microprocessor
` Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle
-100, 133 and 150 MHz operating frequency Consult Factory for latest speeds
-228 Dhrystone2.1 MIPS
-SPECInt95 4.2 SPECfp95 4.5
` System interface optomized for embedded applications
-32-bit system interface lowers total system cost with up to 87.5 MHz operating frequency
-High performance write protocols maximize uncached write bandwidth
-Operates at processor clock divisors 2 through 8
-5V tolerant I/O's
- IEEE 1149.1 JTAG boundary scan
` Integrated on-chip caches
-16KB instruction - 2 way set associative
- 16KB data - 2 way set associative
- Virtually indexed, physically tagged
- Write-back and write-through on per page basis
- Early restart on data cache misses
` Integrated memory management unit
- Fully associative joint TLB (shared by I and D translations)
- 48 dual entries map 96 pages
- Variable page size (4KB to 16MB in 4x increments)
` High-performance floating point unit
- Single cycle repeat rate for common single precision operations and some double precision operations
- Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations
- Single cycle repeat rate for single precision combined multiply-add operation
` MIPS IV instruction set
- Floating point multiply-add instruction increases performance in signal processing and graphics applications
- Conditional moves to reduce branch frequency
- Index address modes (register + register)
` Embedded application enhancements
- Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction
- I and D cache locking by set
- Optional dedicated exception vector for interrupts
`Fully static CMOS design with power down logic
- Standby reduced power mode with WAIT instruction
- 2.5 Watts typical with less than 70 mA standby current
` 128-pin Power Quad-4 package (F22), Consult Factory for package configurationSpecifications
|
Symbol |
Rating |
Range |
Units |
|
TTERM |
Terminal Voltage with respect to GND |
-0.52 to 4.6 |
V |
|
TCASE |
Operating Temperature |
0 to +85 |
°C |
|
TBIAS |
Case Temperature under Bias |
-55 to +125 |
°C |
|
TSTG |
Storage Temperature |
-55 to +125 |
°C |
|
IIN |
DC Input Current |
203 |
mA |
|
IOUT |
DC Output Current |
50 |
mA |
Notes:
1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. VIN minimum = -2.0V for pulse width less than 15nS. VIN maximum should not exceed +5.5 Volts.
3. When VIN < 0V or VIN > Vcc.
4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second.
DescriptionThe ACT5230 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit,an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 32-bit system interface. The ACT5230 can issue both an integer and a floating point instruction in the same cycle.
The ACT5230 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally,the ACT5230 includes two implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place.Described in detail in the QED RM5230 datasheet,,these instructions are integer multiply-accumulate and 3-operand integer multiply.
The ACT5230 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add,sub, logical, shift) and an autonomous multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-operand integer multiply/divide operations, and the program counter(PC).
ACT5230 Data Sheet
