Specifications - Hall-effect current monitor — no external sense resistor required
- Analog output voltage (factory trimmed for gain and offset) proportional to applied current
- External high-side FET gate drive
- 240V*A Power Fault Protection with user-programmable delay
- User programmable Overcurrent Fault Protection with programmable delay
- 1.5 mΩ internal conductor resistance
- Short Circuit Protection isolates failed supply from output in <2 µs
- Active low Fault indicator output signal
- External FET failure detection with active low S1 Short failure indicator output signal
- User controlled soft start / hot-swap function Logic enable input pin
- Logic enable input pin
- 10.8 to 13.2 V, single-supply operation
- 2 kV ESD protection for all pins
The ACS760 combines Allegro® Hall-effect current sense technology with a hot-swap controller resulting in a more efficient integrated controller for 12 V applications. By eliminating the need for a shunt resistor, the I2R losses in the power path are reduced.
When the ACS760 is externally enabled, and the voltage rail is above the internal UVLO threshold, the internal charge pump drives the gate of the external FET. When a fault is detected, the gate is disabled while simultaneously alerting the application that a fault has occurred.
The integrated protection in the ACS760 incorporates three levels of fault protection, which includes a Power Fault with user-programmable delay, a user-programmable Overcurrent Fault threshold with programmable delay, and Short Circuit protection, which disables the gate in less then 2 µs.
Additionally, in the event the external high-side FET fails short, the ACS760 detects the S1 Short failure and immediately disables the gate and alerts the host system. Unlike the three protection faults, cycling the EN pin does not reset the S1 Short failure. Power to the device must be cycled.
Description
The ACS760 combines Allegro® Hall-effect current sense technology with a hot-swap controller resulting in a more efficient integrated controller for 12 V applications. By eliminating the need for a shunt resistor, the I2R losses in the power path are reduced.
When the ACS760 is externally enabled, and the voltage rail is above the internal UVLO threshold, the internal charge pump drives the gate of the external FET. When a fault is detected, the gate is disabled while simultaneously alerting the application that a fault has occurred.
The integrated protection in the ACS760 incorporates three levels of fault protection, which includes a Power Fault with user-programmable delay, a user-programmable Overcurrent Fault threshold with programmable delay, and Short Circuit protection, which disables the gate in less then 2 µs.
Additionally, in the event the external high-side FET fails short, the ACS760 detects the S1 Short failure and immediately disables the gate and alerts the host system. Unlike the three protection faults, cycling the EN pin does not reset the S1 Short failure. Power to the device must be cycled.
ACS760 Data Sheet
