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ACS630MS

Features: • Devices QML Qualified in Accordance with MIL-PRF-38535• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96711 and Intersil' QM Plan• 1.25 Micron Radiation Hardened SOS CMOS• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . ....

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SeekIC No. : 004267897 Detail

ACS630MS: Features: • Devices QML Qualified in Accordance with MIL-PRF-38535• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96711 and Intersil' QM Plan• 1.25 Micr...

ACS630MS Data Sheet

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Part Number:
ACS630MS
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96711 and Intersil' QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55 to +125
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current  1A at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 37ns (Max), 24ns (Typ) 


Pinout

Connection Diagram


Description

The Intersil ACS630MS is a Radiation Hardened 16-bit parallel error detection and correction circuit. It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory read cycle a 22-bit word is taken form memory and checked for errors. Single bit errors in the data words are flagged and corrected.Single bit errors in check words are flagged but not corrected. The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which is output during the error correction cycle.

The ACS630MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened,high-speed, CMOS/SOS Logic Family.

The ACS630MS is supplied in a 28 lead Ceramic Flatpack (K suffix) or a 28 Lead Ceramic Dual-In-Line Package (D suffix).




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