Features: ·3.3 V to 5 V logic supply range
·To 10 MHz data input rate
·High-voltage, high-current outputs
·Darlington current-sink outputs, with improved low-saturation voltages
·CMOS, TTL compatible inputs
·Output transient protection
·Internal pull-down resistors
·Low-power CMOS latchesPinout
SpecificationsOutput Voltage, VCE...........................................50 V
Supply Voltage, VDD.............................................7 V
Input Voltage Range, VIN .......0.3 V to VDD +0.3 V
Continuous Collector Current, IC................... 600 mA
Package Power Dissipation, PD, see Allowable Power
Disspation chart, page 5
Operating Temperature Range
Ambient Temperature, TA..............20°C to +85°C
Storage Temperature, TS ............55°C to +150°CDescriptionThe A6800 and A6801 latched-input BiMOS ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of 4 or 8 data (D type) latches with associated common CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power outputs are bipolar NPN Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface ICs greatly benefit the simplification of computer or microprocessor I/O. The A6800 ICs each contain four latched drivers. A6801 ICs contain eight latched drivers.
The CMOS inputs are compatible with standard CMOS circuits. TTL circuits may mandate the addition of input pull-up resistors. The bipolar Darlington outputs are suitable for directly driving many peripheral/power loads: relays, lamps, solenoids, small DC motors, and so forth.
All devices A6800 and A6801 have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 600mA and can withstand at least 50V in the off state. Because of limitations on package power dissipation, the simultaneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability.
The A6800SA is furnished in a 14-pin DIP with 7.62mm (0.300in.) row centers; the A6800SL and A6801SLW in surface-mountable SOICs; the A6801SA in a 22-pin DIP with 10.16mm (0.400in.) row centers; the A6801SEP in a 28-lead PLCC. These devices are lead (Pb) free, with 100% matte tin plated leadframes.
A6800 Data Sheet
