A416316B

Features:

Organization: 65,536 words X 16 bits
Part Identification: 
 - A416316B
 - A416316B-L (with self-refresh mode)
High speed 
 - 30/35/40 ns RAS  access time 
 - 16/18/20 ns column address access time 
 - 10/11/12 ns  CAS  access time
Low power consumption
  - Operating: 75mA (-30 max)
  - Standby: 3 mA (TTL)  
Separate  CAS  (UCAS ,LCAS ) for byte selection
Self refresh mode
256 refresh cycles, 4 ms refresh interval
Read-modify-write,  RAS -only,  CAS -before- RAS , Hidden refresh capability
TTL-compatible, three-state I/O
JEDEC standard packages
 - 400mil, 40-pin SOJ
 - 400mil, 40/44 TSOP type II package
Single 5V power supply/built-in VBB generator


Pinout




Specifications

Input Voltage (Vin) . . . . . . . . . . . . . . . . . .  . . . . -1.0V to +7.0V
Output Voltage (Vout) . . . . . . . . . . . . . . . . . . . ..-1.0V to +7.0V
Power Supply Voltage (VCC) . . . . . . . . . . . . .. .  -1.0V to +7.0V
Operating Temperature (TOPR) . . . . . . . . . . . . .0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . .. . .  -55°C to +150°C
Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . . . . .. .   50mA
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA


Description

The A416316B is a high performance CMOS Dynamic Random Access Memory organized as 65,536 words X 16 bits. The A416316B is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.
 
The A416316B features a high speed page mode operation in which high speed read, write and read-write are performed on any of the bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe  ( UCAS and  LCAS ) which acts as an output enable independent of RAS . Very fast UCAS and LCAS   to output access time eases system design.
 
All inputs are TTL compatible. Fast Page Mode operation allows random access up to 256 X 16 bits within a page, with cycle time as short as 19/21/23 ns.
 
The A416316B is best suited for graphics, digital signal processing and high performance peripherals.
 
The A416316B is available in JEDEC standard 40-pin plastic SOJ package and 40/44 TSOP type II package.