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A3P015

Features: High Capacity• 15 k to 1 M System Gates• Up to 144 kbits of True Dual-Port SRAM• Up to 300 User I/OsReprogrammable Flash Technology• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process• Live at Power-Up (LAPU) Level 0 Support• Single-Chip Soluti...

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SeekIC No. : 004260273 Detail

A3P015: Features: High Capacity• 15 k to 1 M System Gates• Up to 144 kbits of True Dual-Port SRAM• Up to 300 User I/OsReprogrammable Flash Technology• 130-nm, 7-Layer Metal (6 Copper...

A3P015 Data Sheet

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Part Number:
A3P015
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM-enabled ProASIC®3
devices) via JTAG (IEEE 1532compliant)†
• FlashLock® to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• Bank-Selectable I/O Voltages-up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
    2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS
    2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (*1, *2, *4, *9, and *18 organizations)†
• True Dual-Port SRAM (except *18)
ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices-Cortex-M1 and CoreMP7 Soft Processor Available with or without Debug




Specifications

Symbol
Parameter
Limits
Units
VCC
 DC core supply voltage
0.3 to 1.65
V
VJTAG
 JTAG DC voltage
0.3 to 3.75
V
VPUMP
 Programming voltage
0.3 to 3.75
V
VCCPLL
 Analog power supply (PLL)
0.3 to 1.65
V
VCCI
 DC I/O output buffer supply voltage
0.3 to 3.75
V
VMV
 DC I/O input buffer supply voltage
0.3 to 3.75
V
VI
 I/O input voltage
0.3 V to 3.6 V
(when I/O hot insertion mode is enabled)
0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
V
TSTG 2
 Storage temperature
65 to +150
TJ 2
 Junction temperature
+125
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2.




Description

ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up (LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.

ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. ProASIC3 devices support the ARM7 soft IP core and Cortex-M1 devices. The ARM-enabled devices have Actel ordering numbers that begin with M7A3P (CoreMP7) and M1A3P (Cortex-M1) and do not support AES decryption.






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