9DB202CGLF

• Two 0.7V current mode differential HCSL output pairs1 differential clock input
• CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 140MHz
• Output skew: 110ps (maximum)
• Cycle-to-cycle jitter: 110ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.42ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request

DescriptionThe ICS9DB202 is a high perfromance 1-to-2 Differential-to-HCSL Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter-attenuating ICS9DB202 may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500kHz. This setting offers the best jitter attenuation and is still high enough to pass a triangular input spread spectrum profile. In high bandwidth mode, the PLL bandwidth is at 1MHz and allows the PLL to pass more spread spectrum modulation.

For SerDes which have x10 reference multipliers instead of x12.5 outputs of ICS9DB202 (PCIEX0:1) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1).