DescriptionThe 89PES24N3 is designed as a member of IDT's PRECISE family of PCI express bridging and switching solutions offering the next-generation I/O interconnect standard. 89PES24N3 is a 24-lane, 3-port peripheral chip that performs PCI Express Base switching with a feature set optimized for ...
89PES24N3: DescriptionThe 89PES24N3 is designed as a member of IDT's PRECISE family of PCI express bridging and switching solutions offering the next-generation I/O interconnect standard. 89PES24N3 is a 24-lan...
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The 89PES24N3 is designed as a member of IDT's PRECISE family of PCI express bridging and switching solutions offering the next-generation I/O interconnect standard. 89PES24N3 is a 24-lane, 3-port peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. 89PES24N3 provides high-performance I/O connectivity and switching functions between a PCI Express upstream port and two downstream ports or peer-to-peer switching between downstream ports.
89PES24N3 has six features about its high performance PCI express switch. (1)24 PCI express lanes (2.5Gbps), 3 switch ports. (2)12 GBps (96Gbps) aggregate switching throughput. (3)Low latency cut-through switch architecture. (4)Supports 128 to 2048byte maximum payload size. (5)One virtual channel. (6)Fully compliant with PCI express base specification revision 1.0a. That are all the main features.
Some specifications about 89PES24N3's power management have been concluded into several points as follow. (1)Utilizes advanced low-power design techniques to achieve low typical power consumption. (2)Support PCI express power management interface specification (PCI-PM 1.1). (3)Unused serdes are disabled. (4)Supports advanced configuration and power interface specification, revision 2.0 (ACPI) supporting active link state.
Also some specifications about 89PES24N3's testability and debug are concluded as follow. (1)Support IEEE 1149.6 JTAG which extends the capability of the IEEE 1149.1 standard to include AC-coupled and/or differential nets. (2)Built in pseudo-random bit stream (PRBS) generator. (3)Numerous serdes test modes. (4)Ability to read and write any internal register via the SMBus. (5)Ability to bypass link training and force any link into any mode. (6)Provides statistics and performance counters. (7)Also it has 8 general purpose input output pins and each pin may be individually configured as an input or output. And so on. If you have any question or suggestion or want to know more information about 89PES24N3 please contact us for details. Thank you!