89HPES32H8

High Performance PCI Express Switch
Eight maximum switch ports
• Four main ports each of which consists of eight SerDes
• Each x8 main port can further bifurcate to 2 x4-ports
Thirty-two 2.5 Gbps embedded SerDes
• Supports pre-emphasis and receive equalization on per-port basis
Delivers 128 Gbps (16 GBps) aggregate switching capacity
Low-latency cut-through switch architecture
Support for Max Payload Size up to 2048 bytes
Supports two virtual channels and eight traffic classes
PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
Port arbitration schemes utilizing round robin algorithms
Virtual channels arbitration based on priority
Automatic per port link width negotiation to x8, x4, x2 or x1
Automatic lane reversal on all ports
Automatic polarity inversion on all ports
Supports locked transactions, allowing use with legacy software
Ability to load device configuration from serial EEPROM
Ability to control device via SMBus
Highly Integrated Solution
Requires no external components
Incorporates on-chip internal memory for packet buffering and queueing
Integrates thirty-two 2.5 Gbps embedded full duplex SerDes,8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
Redundant upstream port failover capability
Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC)
Supports optional PCI Express end-to-end CRC checking
Supports optional PCI Express Advanced Error Reporting
Supports PCI Express Hot-Plug
• Compatible with Hot-Plug I/O expanders used on PC motherboards
Supports Hot-Swap
Power Management
Supports PCI Power Management Interface specification,Revision 1.1 (PCI-PM)
• Supports powerdown modes at the link level (L0, L0s, L1, L2/L3 Ready and L3) and at the device level (D0, D3hot)
Unused SerDes disabled
Testability and Debug Features
Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
Ability to read and write any internal register via the SMBus
Ability to bypass link training and force any link into any mode
Provides statistics and performance counters
Thirty-two General Purpose Input/Output pins
Each pin may be individually configured as an input or output
Each pin may be individually configured as an interrupt input
Some pins have selectable alternate functions
Packaged in a 31mm x 31mm 900-ball Flip Chip BGA with 1mm ball spacing

Utilizing standard PCI Express interconnect, the PES32H8 provides he most efficient system interconnect switching solution for applications equiring maximum throughput, low latency, and simple board layout ith a minimum number of board layers. PES32H8 provides 128 Gbps of aggregated, ull-duplex switching capacity through 32 integrated serial lanes, sing proven and robust IDT technology. Each lane provides 2.5 Gbps f bandwidth in both directions and is fully compliant with PCI Express ase specification 1.1.

The PES32H8 is based on a flexible and efficient layered architecture.

The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES32H8 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions.

PES32H8 supports eight Traffic Classes (TCs) and two Virtual Channels (VC) with sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded applications.