89HPES16NT2

High Performance PCI Express Switch
Sixteen PCI Express lanes (2.5Gbps), two switch ports
Delivers 64 Gbps (8 GBps) of aggregate switching capacity
Low latency cut-through switch architecture
Support for Max Payload size up to 2048 bytes
Supports one virtual channel and eight traffic classes
PCI Express Base specification Revision 1.0a compliant
Flexible Architecture with Numerous Configuration Options
Supports automatic per port link width negotiation (x8, x4, x2,or x1)
Static lane reversal on all ports
Automatic polarity inversion on all lanes
Supports locked transactions, allowing use with legacy software
Ability to load device configuration from serial EEPROM
Ability to control device via SMBus
Non-Transparent Port
Crosslink support on NTB port
Four mapping windows supported
• Each may be configured as a 32-bit memory or I/O window
• May be paired to form a 64-bit memory window
Interprocessor communication
• Thirty-two inbound and outbound doorbells
• Four inbound and outbound message registers
• Two shared scratchpad registers
Allows up to sixteen masters to communicate through the nontransparent port
No limit on the number of supported outstanding transactions through the non-transparent bridge
Completely symmetric non-transparent bridge operation allows similar/same configuration software to be run
Supports direct connection to a transparent or non-transparent port of another switch
Highly Integrated Solution
Requires no external components
Incorporates on-chip internal memory for packet buffering and queueing
Integrates sixteen 2.5 Gbps embedded full duplex SerDes, 8B/ 10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement  nd-to-end CRC (ECRC)
Supports ECRC pass-through
Supports Hot-Swap
Power Management
Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM)
Unused SerDes are disabled
Testability and Debug Features
Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
Ability to read and write any internal register via the SMBus
Ability to bypass link training and force any link into any mode
Provides statistics and performance counters
Two SMBus Interfaces
Slave interface provides full access to all software-visible registers by an external SMBus master
Master interface provides connection for an optional serial EEPROM used for initialization
Master interface is also used by an external Hot-Plug I/O expander
Master and slave interfaces may be tied together so the switch can act as both master and slave
Eight General Purpose Input/Output pins
Packaged in a 23mm x 23mm 484-ball BCG with 1mm ball spacing

Utilizing standard PCI Express interconnect, the PES16NT2 provides the most efficient high-performance I/O onnectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. With support for non-transparent bridging, the PES16NT2 is part of the IDT PCIe System Interconnect Products that target multi-host and intelligent I/O applications requiring inter-domain communication.

The PES16NT2 provides 64 Gbps (8 GBps) of aggregated, full-duplex switching capacity through 16 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.0a.

The PES16NT2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link, and Transaction layers in compliance with PCI Express Base specification Revision 1.0a. The PES16NT2 can operate either as a store  nd forward or cutthrough switch depending on the packet size and is designed to switch memory and I/O  ransactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource   anagement.