87LPC768

Features:

An accelerated 80C51 CPU provides instruction cycle times of 300?00 ns for all instructions except multiply and divide when executing at 20 MHz. Execution at up to 20 MHz when
V_DD = 4.5 V to 6.0 V, 10 MHz when V_DD = 2.7 V to 6.0 V.
Four-channel 10-bit Pulse Width Modulator
Four-channel multiplexed 8-bit A/D converter. Conversion time of 9.3mS at fosc = 20 MHz.
2.7 V to 6.0 V operating range for digital functions.
4 kbytes EPROM code memory.
128 byte RAM data memory.
32-byte customer code EPROM allows serialization of devices, storage of setup parameters, etc.
Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon timer overflow.
Two analog comparators.
Full duplex UART.
I²C communication port.
Eight keypad interrupt inputs, plus two additional external interrupt inputs.
Four interrupt priority levels.
Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog timeout time is selectable from 8 values.
Active low reset. On-chip power-on reset allows operation with no external reset components.
Low voltage reset. One of two preset low voltage levels may be selected to allow a graceful system shutdown when power fails. May optionally be configured as an interrupt.
Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator, allowing it to perform an oscillator fail detect function.
Configurable on-chip oscillator with frequency range and RC oscillator options (selected by user programmed EPROM bits). The RC oscillator option allows operation with no external oscillator components.
Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only.
Selectable Schmitt trigger port inputs.
LED drive capability (20 mA) on all port pins.
Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.
15 I/O pins minimum. Up to 18 I/O pins using on-chip oscillator and reset options.
Only power and ground connections are required to operate the 87LPC768 when fully on-chip oscillator and reset options are selected.
Serial EPROM programming allows simple in-circuit production coding. Two EPROM security bits prevent reading of sensitive application programs.
Idle and Power Down reduced power modes. Improved wakeup from Power Down mode (a low interrupt input starts execution). Typical Power Down current is 1 mA.
20-pin DIP and SO packages.

Pinout




Specifications

PARAMETER	RATING	UNIT
Operating temperature under bias	55 to +125
Storage temperature range	65 to +150
Voltage on RST/VPP pin to VSS	0 to +11.0	V
Voltage on any other pin to VSS	0.5 to VDD+0.5 V	V
Maximum IOL per I/O pin	20	mA
Power dissipation (based on package heat transfer limitations, not device power consumption)	1.5	W

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_ss unless otherwise noted.


Description

The 87LPC768 is a 20-pin single-chip microcontroller designed for low pin count applications demanding high-integration, low cost solutions over a wide range of performance requirements. A member of the Philips low pin count family, the 87LPC768 offers programmable oscillator configurations for high and low speed
crystals or RC operation, wide operating voltage range, programmable port output configurations, selectable Schmitt trigger inputs, LED drive outputs, and a built-in watchdog timer. The 87LPC768 is based on an accelerated 80C51 processor architecture that executes instructions at twice the rate of standard 80C51 devices.