Features: *80C51 based architecture
8k * 8 ROM (83C575)
8k 8 EPROM (87C575)*
ROMless (80C575)
256 * 8 RAM
Three 16-bit counter/timers
Programmable Counter Array
Enhanced UART
Boolean processor
Oscillator fail detect
Low active reset
Asynchronous low port reset
Schmitt trigger inputs
4 analog comparators
Watchdog timer
Low VCCdetect
*Memory addressing capability
64k ROM and 64k RAM
*Power control modes:
Idle mode
Power-down mode
*CMOS and TTL compatible
*4.0 to 16MHz
*Extended temperature ranges
*OTP package availablePinoutSpecifications
PARAMETER |
RATING |
UNIT |
Operating temperature under bias |
55to +125 |
|
Storage temperature range |
-65 to +150 |
|
Voltage on EA/V pin to V |
0 to +13.0 |
V |
Voltage on any other pin to VSS |
0.5 to +6.5 |
V |
Maximum IOL per I/O pin |
15 |
mA |
Power dissipation (based on package heat transfer limitations, not device power consumption) |
1.5 |
W |
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only an
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.DescriptionThe Philips 80C575/83C575/87C575 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The Philips CMOS technology combines the high speed and density characteristics of HMOS 80C575/83C575/87C575 with the low power attributes of CMOS. Philips epitaxial substrate minimizes latch-up sensitivity.
The 8XC575 contains an 8k × 8 ROM (83C575) EPROM (87C575), a 256 × 8 RAM 32 I/O lines, three 16-bit counter/timers, a Programmable Counter Array (PCA), a seven-source, two-priority level nested interrupt structure, an enhanced UART, four analog comparators, power-fail detect and oscillator fail detect circuits, and on-chip oscillator and clock circuits.
In addition, the 8XC575 has a low active reset, and the port pins are reset to a low level. There is also a fully configurable watchdog timer, and internal power on clear circuit. The part 80C575/83C575/87C575 includes idle mode and power-down mode states for reduced power consumption.