Specifications | Temperature | I |
| Voltage | 3.3 V |
| Package | TQFP 52 |
| Speed | NA |
Description10 LVCMOS OUT BUFFER/DIVIDER
ICS87949I Features
- 15 single ended LVCMOS outputs, 7W typical output impedance
- Selectable LVCMOS or LVPECL clock inputs
- CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL
- PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
- Maximum output frequency: 160MHz
- Output skew: 350ps (maximum)
- Part-to-part skew: 2.75ns (maximum)
- 3.3V supply modes
- -40°C to 85°C ambient operating temperature
Description
The ICS87949I is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS? family of High Performance Clock Solutions from IDT. The ICS87949I has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50W series or parallel terminated transmission lines. The effective fanout of ICS87949I can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs of ICS87949I can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input of ICS87949I, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.
The ICS87949I is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply mode. Guaranteed bank, output and part-to-part skew characteristics make the ICS87949I ideal for those clock distribution applications demanding well defined performance and repeatability.
87949AYILF Data Sheet
