87946AYI-01LFT

• 10 single ended LVCMOS outputs, 7W typical output impedance
• Selectable CLK0 and CLK1 LVCMOS clock inputs
• CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL
• Maximum input/output frequency: 150MHz
• Output skew: 350ps (maximum)
• 3.3V input, 3.3V outputs
• -40°C to 85°C ambient operating temperature

Description
The ICS87946I is a low skew, ÷1, ÷2 LVCMOS Clock Generator and a member of the HiPerClockS? family of High Performance Clock Solutions from IDT. The ICS87946I has two selectable single ended clock inputs. The single ended clock inputs accept LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50W series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines.

The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs of ICS87946I can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input of ICS87946I, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.