874S02BMIT

• One differential LVDS output pair designed to meet or exceed the requirements of ANSI TIA/EIA-644, One differential feedback output pair
• Differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL
• Output frequency range: 62.5MHz to 1GHz
• Input frequency range: 62.5MHz to 1GHz
• VCO range: 500MHz to 1GHz
• External feedback for "zero delay" clock regeneration with configurable frequencies
• Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 26ps (typical)
• Output skew: 4ps (typical)
• Static phase offset: 98ps (typical), 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant packages

Description
The ICS874S02I is a highly versatile 1:1 LVDS Clock Generator and a member of the HiPerClockS? family of High Performance Clock Solutions from IDT. The ICS874S02I has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 62.5MHz to 1GHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the ICS874S02I to achieve "zero delay" between the input clock and the output clock. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.