8741004AGLFT

• Differential LVDS and (2) HCSL output pairs
• (1) Differential clock input
• CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 15ps (typical)3.3V operating supply
• 3 bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request

Description
The ICS8741004 is a high performance Differential-to-LVDS/HCSL Jitter Attenuator designed for use in PCI Express? systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS8741004 has 3 PLL bandwidth modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while provid-ing good jitter attenuation. 800kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower band-width modes. Because some 2.5Gb serdes have x20 multipliers while others have x25 multipliers, the ICS8741004 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the FSEL pins.

The ICS8741004 uses ICS 3rd Generation FemtoClockTM PLL technology to achive the lowest possible phase noise. The ICS8741004 is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.