874003AG-02LF

Packaging :
Output Level : LVDS
Package / Case : TSSOP-20
Input Level : HCSL, LVDS, LVHSTL, LVPACL, SSTL
Max Input Freq : 128 MHz
Number of Outputs : 3
Supply Voltage - Max : 3.465 V
Supply Voltage - Min : 3.135 V
Max Output Freq : 320 MHz


Specifications

Temperature C Voltage 3.3 V Package TSSOP 20 Speed NA Output Supply Voltage (VDDO) Output Style Min. Input Frequency Core Supply Voltage (VDD) No. of Outputs No. of Inputs Input Style Max. Output Frequency Min. Output Frequency Max. Input Frequency Temp. Grade


Description

3 LVDS - JITTER ATTEN GEN
ICS874003 Features

• Three Differential LVDS output pairs
• One Differential clock input
• CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 35ps (maximum)
• 3.3V operating supply
• 3 bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant packages

Description
The ICS874003 is a high performance Differential-to-LVDS Jitter Attenuator designed for use in PCI Expres systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003 has 3 PLL bandwidth modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will pro-vide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 800kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have than x25 multipliers, the ICS874003 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the FSEL pins.

The ICS874003 uses ICS 3rd Generation FemtoClockTM PLL technology to achive the lowest possible phase noise. The ICS874003 is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.