873995AYLF

Specifications Temperature C Voltage 3.3 V Package PTQFP 48 Speed NA Output Style Core Supply Voltage (VDD) ...

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SeekIC No. : 004257039 Detail

873995AYLF: Specifications Temperature C Voltage 3.3 V Package PTQFP 48 Speed NA ...

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Part Number:
873995AYLF
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Specifications

Temperature C Voltage 3.3 V Package PTQFP 48 Speed NA Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade Multiplication/Divide Value


Description

6 LVPECL OUT MUX
ICS873995 Features
  • Six differential 3.3V LVPECL outputs
  • Selectable differential clock inputs
  • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Input clock frequency range: 49MHz to 213.33MHz
  • Output clock frequency range: 49MHz to 640MHz
  • VCO range: 490MHz to 640MHz
  • External feedback for "zero delay" clock regeneration with configurable frequencies
  • Output skew: 70ps (maximum) (design target)
  • RMS phase jitter (1.875MHz - 20MHz): <1ps (design target) assuming a low phase noise reference clock input
  • 3.3V supply voltage
  • 0°C to 70°C ambient operating temperature
  • Available in both standard and lead-free RoHS compliant packages

Description
The ICS873995 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the HiPerClockS? family of low jitter/phase noise devices from IDT. The ICS873995 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are critical. The ICS873995 receives two differential LVPECL clock signals from which it generates 6 LVPECL clock outputs with "zero" delay. The output divider and feedback divider selections also allow for frequency multiplication or division.

The ICS873995 Dynamic Clock Switch (DCS) circuit continuously monitors both input clock signals. Upon detection of a failure (input clock stuck LOW or HIGH for at least 1 period), INP_BAD for that clock will be set HIGH. If that clock is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output of ICS873995 phase disturbance.

The low jitter characteristics of ICS873995 combined with input clock monitor-ing and automatic switching from bad to good input clocks make the ICS873995 an ideal choice for mission critical applications that utilize 1G or 10G Ethernet or 1G/4G/10G Fibre Channel.




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