8702BYLF

• Twenty LVCMOS outputs, 7W typical output impedance
• One differential clock input pair
• CLK, nCLK supports the following input types:
• LVPECL, CML, SSTL
• Maximum output frequency up to 250MHz
• Translates any differential input signal (LVPECL, LVHSTL, LVDS) to LVCMOS levels without external bias networks
• Translates any single-ended input signal to LVCMOS levels with a resistor bias on nCLK input
• Bank enable logic allows unused banks to be disabled in reduced fanout applications
• Output skew: 200ps (maximum)
• Bank skew: 150ps (maximum)
• Part-to-part skew: 650ps (maximum)
• Multiple frequency skew: 250ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
• Available in both standard and lead-free RoHS compliant packages

DescriptionThe ICS8702 is a low skew, 1, 2 Differential-to-LVCMOS Clock Generator and a member of the HiPerClockS family of High Performance Clock Solutions from ICS. The ICS8702 is designed to translate any differential signal levels to LVCMOS levels. True or inverting, single-ended to LVCMOS translation can be achieved with a resistor bias on the nCLK or CLK inputs, respectively. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.

The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the 1, 2 or a combination of 1 and 2 modes. The bank enable inputs of ICS8702, BANK_EN0:1, supports enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the enabling and disabling of all outputs simultaneously.

The ICS8702 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output, multiple frequency and part-to-part skew characteristics make the ICS8702 ideal for those clock distribution applications demanding well defined performance and repeatability.