8624BYLF

Specifications

Temperature C Voltage 3.3 V Package TQFP 32 Speed NA Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade Multiplication/Divide Value


Description

5 LVHSTL OUT ZDB
ICS8624 Features

• Fully integrated PLL
• 5 differential HSTL outputs
• Selectable differential CLKx, nCLKx input pairsCLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for "zero delay" clock regeneration
• Cycle-to-cycle jitter: 25ps (maximum)
• Output skew: 25ps (maximum)
• Static phase offset: ±100ps
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package fully RoHS compliant

Description
The ICS8624 is a high performance, 1-to-5 Differential-to-HSTL zero delay buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from IDT. The ICS8624 has two selectable clock input pairs. The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 700MHz. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 700MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications.