8602BYLF

Specifications

Temperature C Voltage 3.3 V Package TQFP 32 Speed NA Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade Multiplication/Divide Value


Description

9 LVCMOS OUT ZDB
ICS8602 Features

• Fully integrated PLL
• 9 LVCMOS/LVTTL outputs, 7W typical output impedance
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for "zero delay" clock regeneration with configurable frequencies
• Cycle-to-cycle jitter: 36ps (typical)
• Output skew: 125ps (maximum)
• Static Phase Offset: TBD±100ps (typical)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature

Description
The ICS8602 is a high performance, low skew, 1-to-9 Differential-to-LVCMOS/LVTTL Zero Delay Buffer and a member of the HiPerClockS? family of High Performance Clocks Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 500MHz. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The device is designed only for 1:1 input/output frequency ratios. The output divider allows a wide input/output frequency range with the 250MHz to 500MHz VCO. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.The low impedance LVCMOS/LVTTL outputs are designed to drive 50W series or parallel terminated transmission lines. The effective fanout can be doubled by utilizing the ability of the outputs to drive two series terminated lines. The differential reference clock input will accept any differential signal levels.