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857DSL

Features: * Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) - The core performs branch prediction with conditional prefetch, without conditional execution - 4- or 8-Kbyte data cache and 4- or 16-Kbyte instru...

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SeekIC No. : 004256515 Detail

857DSL: Features: * Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) - The core performs branch prediction with cond...

857DSL Data Sheet

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Part Number:
857DSL
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

* Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with  thirty-two 32-bit general-purpose registers (GPRs)
   - The core performs branch prediction with conditional prefetch, without conditional execution
   - 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
   16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte  instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative  with 128 sets.
   8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data  cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.
  Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)  cache blocks.
  Caches are physically addressed, implement a least recently used (LRU) replacement  algorithm, and are lockable on a cache block basis.
   - MMUs with 32-entry TLB, fully associative instruction and data TLBs
   - MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address  spaces and 16 protection groups
   - Advanced on-chip-emulation debug mode
* The MPC862/857T/857DSL provides enhanced ATM functionality over that of the MPC860SAR.  The MPC862/857T/857DSL adds major new features available in "enhanced SAR" (ESAR) mode,  including the following:
   - Improved operation, administration and maintenance (OAM) support
   - OAM performance monitoring (PM) support
   - Multiple APC priority levels available to support a range of traffic pace requirements
   - ATM port-to-port switching capability without the need for RAM-based microcode
   - Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability


Specifications

Rating Symbol Value Unit Max Freq
(MHz)
Supply voltage1
 VDDH -0.3 to 4.0 V -
VDDL -0.3 to 4.0 V -
KAPWR -0.3 to 4.0 V -
VDDSYN -0.3 to 4.0 V -

Input voltage2		 Vin GND-0.3 to VDDH V -



Description

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC862/857T/857DSL family (refer to Table 1 for a list of devices). The MPC862P, which contains a PowerPC(TM) core processor, is the superset device of the MPC862/857T/857DSL family.


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