854S204BGILFT

Specifications

Package TSSOP 16 Speed NA Temperature I Voltage 3.3 V Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade


Description

DUAL, 1-TO-2 FANOUT BUFFER
ICS854S204I Features

• Two differential LVDS or LVPECL output banks
• Two differential clock input pairs
• CLKx, nCLKx pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: >3GHz
• Translates any single ended input signal to LVDS levels with resistor bias on nCLKx inputs
• Output skew: <25ps (typical) design target
• Bank skew: <50ps (typical) design target
• Propagation delay: TBD
• Additive phase jitter, RMS: 0.15ps (typical)
• Full 3.3V or 2.5V power supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages

Description
The ICS854S204I is a low skew, high performance dual, 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from IDT. The CLKx, nCLKx pairs can accept most standard differential input levels. The ICS854S204I is characterized tooperate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the ICS854S204I ideal for those clock distribution applications demanding well defined performance and repeatability.