8543BGI

Clock Buffer 1-4 Differential to LVDS Fanout Buffer

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SeekIC No. : 00312688 Detail

8543BGI: Clock Buffer 1-4 Differential to LVDS Fanout Buffer

floor Price/Ceiling Price

US $ 9.45~11.63 / Piece | Get Latest Price
Part Number:
8543BGI
Mfg:
IDT
Supply Ability:
5000

Price Break

  • Qty
  • 0~1
  • 1~10
  • 10~25
  • 25~50
  • Unit Price
  • $11.63
  • $10.75
  • $9.79
  • $9.45
  • Processing time
  • 15 Days
  • 15 Days
  • 15 Days
  • 15 Days
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Total Cost: $ 0.00

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Upload time: 2024/10/30

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Product Details

Quick Details

Number of Outputs : 4 Propagation Delay (Max) : 2.6 ns
Supply Voltage - Max : 3.465 V Supply Voltage - Min : 3.135 V
Maximum Operating Temperature : + 85 C Minimum Operating Temperature : - 40 C
Package / Case : TSSOP-20    

Description

Max Input Freq :
Maximum Power Dissipation :
Packaging :
Maximum Operating Temperature : + 85 C
Minimum Operating Temperature : - 40 C
Number of Outputs : 4
Supply Voltage - Max : 3.465 V
Supply Voltage - Min : 3.135 V
Propagation Delay (Max) : 2.6 ns
Package / Case : TSSOP-20


Specifications

Temperature I Voltage 3.3 V Package TSSOP 20 Speed NA


Description

4 LVDS OUT BUFFER
ICS8543 Features
  • 4 differential LVDS outputs
  • Selectable differential CLK, nCLK or LVPECL clock inputs
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
  • Maximum output frequency: 800MHz
  • Translates any single ended input signal to LVDS levels with resistor bias on nCLK input
  • Output skew: 40ps (maximum)
  • Part-to-part skew: 500ps (maximum)
  • Propagation delay: 2.6ns (maximum)
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Lead-Free package available
  • Industrial temperature information available upon request

Description
The ICS8543 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100W. The ICS8543 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the ICS8543 ideal for those applications demanding well defined performance and repeatability.




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