85411AMLFT

Specifications

Temperature C Voltage 3.3 V Package SOIC 8 Speed NA Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade


Description

85411AMLFT 2 LVDS OUT BUFFER

Two differential LVDS outputs

One differential CLK, nCLK clock input

CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

Maximum output frequency: 650MHz

Translates any single ended input signal to LVDS levels with resistor bias on nCLK input

Output skew: 20ps (maximum)

Part-to-part skew: 250ps (maximum)

Additive phase jitter, RMS: 0.05ps (typical)

Propagation delay: 2.5 ns (maximum)

3.3V operating supply

0°C to 70°C ambient operating temperature

Available in both standard (RoHS 5) and lead free (RoHS 6) packages