8516FYLFT

Specifications

Temperature C Voltage 3.3 V Package TQFP 48 Speed NA Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade


Description

16 LVDS OUT BUFFER
ICS8516 Features

• 16 Differential LVDS outputsCLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 700MHz
• Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS with resistor bias on nCLK input
• Multiple output enable inputs for disabling unused outputs in reduced fanout applications
• LVDS compatible
• Output skew: 90ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 2.4ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperatureLead-Free package available
• Industrial temperature information available upon request

Description
The ICS8516 is a low skew, high performance 1-to-16 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS? family of High Performance Clock Solutions from IDT. The ICS8516 CLK, nCLK pair can accept any differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS8516 provides a low power, low noise, point-to-point solution for distributing clock signals over controlled impedances of 100W.

Dual output enable inputs allow the ICS8516 to be used in a 1-to-16 or 1-to-8 input/output mode.

Guaranteed output and part-to-part skew specifications make the ICS8516 ideal for those applications demanding well defined performance and repeatability.