8305AGLF

Max Input Freq :
Maximum Power Dissipation :
Packaging :
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C
Number of Outputs : 4
Supply Voltage - Max : 3.465 V
Supply Voltage - Min : 3.135 V
Package / Case : TSSOP-16
Propagation Delay (Max) : 2.8 ns


Specifications

Temperature C Voltage 3.3 V Package TSSOP 16 Speed NA Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade


Description

4 LVCMOS OUT BUFFER
ICS8305 Features

• Four LVCMOS/LVTTL outputs
• Selectable differential or LVCMOS/LVTTL clock inputs
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS_CLK supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 350MHz
• Output skew: 35ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Additive phase jitter, RMS: 0.04ps (typical)
• 3.3V core, 3.3V, 2.5V, 1.8V or 1.5V output operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard and lead-free RoHS-compliant packages

Description
The ICS8305 is a low skew, 1-to-4, Differential/LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.

Guaranteed output and part-to-part skew characteristics make the ICS8305 ideal for those applications demanding well defined performance and repeatability.