82815GMCH

 Processor/Host Bus Support
- Intel Pentium III processor and Intel® Celeron™ Processor in FC-PGA package
- Supports processor 370-Pin Socket
- Supports 32-Bit System Bus Addressing
- 4 deep in-order queue; 4 or 1 deep request queue
- Supports Uni-processor systems only
-In-order and Dynamic Deferred Transaction Support
-66/100/133MHz System Bus Frequency
-GTL+ I/O Buffer
 Integrated SDRAM Controller
 -32 MB to 512 MB using 16Mb/64Mb/128Mb/256Mb technology
 -Supports up to 3 double sided DIMMs at 100 MHz system memory bus
 -Supports up to 2 double sided or 3 single sided DIMMs at 133 MHz system memory bus.
 -64-bit data interface
 -100/133 MHz system memory bus frequency
 -Support for Asymmetrical SDRAM addressing only
 -Support for x8 and x16 SDRAM device width
 -Unbuffered, Non-ECC SDRAM only supported
 -Refresh Mechanism: CBR ONLY supported
 -Enhanced Open page arbitration SDRAM paging scheme
 -Suspend to RAM support
 Accelerated Graphics Port (AGP) Interface Multiplexed with Internal Graphics
 -Supports a single AGP device via a connector
 -Supports AGP 2.0 including 4x AGP data transfers
 -AGP Universal Connector support via dual mode buffers to allow AGP 2.0 3.3V or 1.5V signaling
 -AGP PIPE# or SBA initiated accesses to SDRAM not snooped
 -AGP FRAME# initiated accesses to SDRAM are snooped
 -High priority access support
 -Hierarchical PCI configuration mechanism
 -Delayed transaction support for AGP-to-SDRAM reads that can not be serviced immediately
 Arbitration Scheme and Concurrency
 -Intelligent Centralized Arbitration Model for Optimum Concurrency Support
 -Concurrent operations of processor and System busses supported via dedicated arbitration and data buffering
 Data Buffering
 -Distributed Data Buffering Model for optimum concurrency
 -SDRAM Write Buffer with read-around-write capability
 -Dedicated processor SDRAM, hub interface-SDRAM and Graphics-SDRAM Read Buffers
 Power Management Functions
 -SMRAM space remapping to A0000h (128 KB)
 -Optional Extended SMRAM space above 256 MB,additional 512 KB / 1MB TSEG from Top of Memory,cacheable
 -Stop Clock Grant and Halt special cycle translation from the host to the hub interface
 -ACPI Compliant power management
 -APIC Buffer Management
 -SMI, SCI, and SERR error indication
 Integrated Graphics Controller Multiplexed with AGP Controller
 -3D Hyper Pipelined Architecture
    --Parallel Data Processing (PDP)
    --Precise Pixel Interpolation (PPI)
  -Full 2D H/W Acceleration
  -Motion Video Acceleration
  -Supports 133 MHz System Memory while running in non-CPC mode
 3D Graphics Visual Enhancements
  -Flat & Gouraud Shading
  -Mip Maps with Trilinear and Anisotropic Filtering
  -Full Color Specular
  -Fogging Atmospheric Effects
  -Z Buffering
  -3D Pipe 2D Clipping
  -Backface Culling
 3D Graphics Texturing Enhancements
  -Per Pixel Perspective Correction Texture Mapping
  -Texture Compositing
  -Texture Color Keying/Chroma Keying
 Digital Video Output
  -85 MHz Flat Panel Monitor/Digital CRT Interface Or Digital Video Output for use with a external TV encoder
 Display
  -Integrated 24-bit 230 MHz RAMDAC
  -Gamma Corrected Video
  -DDC2B Compliant
 2D Graphics
  -Up to 1600x1200 in 8-bit Color at 85 Hz Refresh
  -Hardware Accelerated Functions
  -3 Operand Raster BitBLTs
  -64x64x3 Color Transparent Cursor
 Arithmetic Stretch Blitter Video
  -H/W Motion Compensation Assistance for S/W MPEG2 Decode
  -Software DVD at 30 fps
  -Digital Video Out Port
  -NTSC and PAL TV Out Support
  -H/W Overlay Engine with Bilinear Filtering
  -Independent gamma correction, saturation, brightness & contrast for overlay
 Integrated Graphics Memory Controller
  -Intel^® D.V.M. Technology
 Display Cache Interface multiplexed on the AGP interface
  -32-bit data interface
  -133 MHz SDRAM interface only.
  -Flexible AGP In-Line Memory Module (AIMM) Implementation
  -Support for 2 1Mx16, or 1 2Mx32 on AIMM card
  -4 MB maximum addressable
 Supporting I/O Bridge
  -82801AA I/O Controller Hub (ICH)
  -82801BA I/O Controller Hub (ICH2)
 Packaging/Power
  -544 BGA
  -1.85V core with 3.3V CMOS I/O

82815GMCH provides a detailed description of the GMCH signals. The signals are arranged in functional groups according to their associated interface. The states of all of the signals during reset are provided in the System Reset section.

The 82815GMCH symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When 82815GMCH is not present after the signal name the signal is asserted when at the high voltage level.