82596SX

Features: Performs Complete CSMACD Medium Access Control (MAC) Functions Independently of CPU --IEEE 8023 (EOC) Frame DelimitingSupports Industry Standard LANsIEEE TYPE 10BASE-T (TPE) --IEEE TYPE 10BASE5 (Ethernet) --IEEE TYPE 10BASE2 (Cheapernet) --IEEE TYPE 1BASE5 (StarLAN)and the Proposed Stand...

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82596SX Picture
SeekIC No. : 004255618 Detail

82596SX: Features: Performs Complete CSMACD Medium Access Control (MAC) Functions Independently of CPU --IEEE 8023 (EOC) Frame DelimitingSupports Industry Standard LANsIEEE TYPE 10BASE-T (TPE) --IEEE TYPE 10...

floor Price/Ceiling Price

Part Number:
82596SX
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/11/21

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Product Details

Description



Features:

Performs Complete CSMACD Medium Access Control (MAC) Functions Independently of CPU
   --IEEE 8023 (EOC) Frame Delimiting
Supports Industry Standard LANsIEEE TYPE 10BASE-T (TPE)
   --IEEE TYPE 10BASE5 (Ethernet)
   --IEEE TYPE 10BASE2 (Cheapernet)
   --IEEE TYPE 1BASE5 (StarLAN)and the Proposed Standard TYPE 10BASE-F
   --Proprietary CSMACD Networks Up to 20 Mbs
On-Chip Memory Management
   --Automatic Buffer ChainingBuffer Reclamation after Receipt of
   --Bad Frames Optional Save Bad Frames
   --32-Bit Segmented or Linear (Flat) Memory Addressing Formats
82586 Software Compatible
Optimized CPU Interface
   --82596DX Bus Interface Optimized to Intel's 32-Bit i386TMDX
   --82596SX Bus Interface Optimized to Intel's 16-Bit i386TM SX
   --Supports Big Endian and Little Endian Byte Ordering
High-Performance 16-32-Bit Bus
   --Master Interface
   --66-MBs Bus Bandwidth
   --33-MHz Clock Two Clocks Per Transfer
   --Bus Throttle Timers
   --Transfers Data at 100% of Serial Bandwidth
   --128-Byte Receive FIFO 64-Byte
   --Transmit FIFO
Network Management and Diagnostics
   --Monitor Mode
   --32-Bit Statistical Counters
Self-Test Diagnostics
Configurable Initialization Root for Data Structures
High-Speed 5-V CHMOS IV Technology
132-Pin Plastic Quad Flat Pack (PQFP) and PGA Package



Pinout

  Connection Diagram  Connection Diagram  Connection Diagram  Connection Diagram


Specifications

StorageTemperature .......................-65to +150
CaseTemperatureunderBias ............-65to +110
Supply Voltage
    withRespecttoVSS............................0.5Vto +6.5V
VoltageonOtherPins ......................-0.5VtoVCC 0.5V




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