Features: PCI Features
`PCI-X Revision 1.0a support for frequencies up to 133 MHz
`Multi-function PCI device
`PCI Revision 2.2 support for 32-bit wide or 64-bit wide interface at 33 MHz and 66 MHz
`Algorithms that optimally use advanced PCI, MWI,MRM, and MRL commands as well as PCI-X MRD, MRB, and MWB commands
MAC Specific Features
`Low-latency transmit and receive queues
`IEEE 802.3x compliant flow control support with software controllable pause times and threshold values
`Caches up to 64 packet descriptors in a single burst
`Programable host memory receive buffers (256 Bytes to 16 Kbytes) and cache line size (16 Bytes to 256 Bytes)
`Wide, optimized internal data path architecture (128 bits)
`Dual 64 Kbytes configurable Transmit and Receive FIFO buffers
`Descriptor ring management hardware for transmit and receive
`Optimized descriptor fetching and write-back mechanisms
`Mechanism available for reducing interrupts generated by transmit and receive operations
`Support for transmission and reception of packets up to 16 Kbytes
PHY Specific Features
`Integrated PHY for 10/100/1000 Mbps full and half duplex operation
`IEEE 802.3ab Auto-Negotiation support
`IEEE 802.3ab PHY compliance and compatibility
`State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and crosstalk cancellation
`PHY ability to automatically detect polarity and cable lengths and MDI versus MDI-X cable at all speeds
Host Offloading Features
`Transmit and receive IP, TCP and UDP checksum offloading capabilities
`Transmit TCP segmentation
`Advanced packet filtering
`IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags
`Descriptor ring management hardware for transmit and receive
`16-Kbyte jumbo frame support
`Interrupt coalescing (multiple packets per interrupt)
Manageability Features
`Manageability features on both ports: SMB port, ASF 1.0, ACPI, Wake on LAN, and PXE
`On-board SMB port
`Preboot eXecution Environment (PXE) Flash interface support (32-bit nd 64-bit)
`Compliance with PCI Power Management 1.1 and
`ACPI 2.0 register set compliant including:
• D0 and D3 power states
• Network Device Class Power Management Specification 1.1
• PCI Specification 2.2
`SNMP and RMON statistic counters
`SDG 3.0, WfM 2.0, and PC2001 compliance
`Wake on LAN support
Additional Device Features
`Two complete gigabit Ethernet connections in a single device
`Eight activity and link indication outputs that directly drive LEDs
`Internal PLL for clock generation (use either a 25 MHz crystal or a 25 MHz oscillator)
`JTAG (IEEE 1149.1) Test Access Port built in silicon
`On-chip power control circuitry
`Eight software definable pins
`Supports little endian byte ordering for both 32 and 64 bit systems and big endian byte ordering for 64 bit systems
`Provides loopback capabilities
`Single-pin LAN disable function
Technology Features
`364-pin Ball Grid Array (BGA) package
`Footprint compatible with the 82544GC, 82545EM, and 82545GM single port gigabit Ethernet controllers
`Implemented in 0.15u CMOS process
`0 to 55 (maximum) operating temperature Heat sink or forced airflow not required 65 to 140 storage temperature range
`3.3 V PCI signaling with an average power dissipation of 3.5 W
Specifications
|
Symbol |
Parameter |
Min |
Max |
Unit |
| VDD (3.3) |
DC supply voltage on VDDD or
AVDDH with respect to VSS |
VSS - 0.5 |
4.6 |
V |
| VDD (2.5) |
DC supply voltage on AVDDL with
respect to VSS |
VSS - 0.5 |
4.6 or
VDD (2.5) + 0.5b |
V |
| VDD (1.5) |
DC supply voltage on DVDD with
respect to VSS |
VSS - 0.5 |
4.6 or
VDD (2.5) + 0.5c |
V |
| VDD |
DC supply voltage |
VSS - 0.5 |
4.6 |
V |
| VI / VO |
LVTTL input voltage |
VSS - 0.5 |
4.6 |
V |
| VI / VO |
5 V compatible input voltage |
VSS - 0.5 |
4.6 |
V |
| IO |
DC output current (by cell type):
IOL = 3 mA
IOL = 6 mA
IOL - 12 mA |
|
10
20
40 |
mA |
| TSTG |
Storage temperature range |
-40 |
125 |
|
| |
ESD per MIL_STD-883 Test Method 3015, Specification 2001V Latchup Over/Undershoot: 150 mA, 125 |
|
VDD overstress:
VDD(3.3)(7.2 V) |
V |
a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are exceeded. These values should not be used as the limits for normal device operations.
b. The maximum value is the lesser value of 4.6 V or VDD(2.5) + 0.5 V. This specification applies to biasing the device to a steady state for an indefinite duration. During normal device power-up, explicit power sequencing is not required.
c. The maximum value is the lesser value of 4.6 V or VDD(2.5) + 0.5 V.
82546EB Data Sheet
