Features: Full IEEE 802.3ab compliant -Auto-Negotiation of speed, duplex, and flow control configuration
32/64-bit 33/66 MHz, PCI Rev 2.2 compliant host interface
Host interface compliant to the PCI-X addendum, revision 1.0a, from 50 MHz to 133 MHz
Offers both hardware and software based IEEE 802.3z Auto-Negotiation and Link
Setup for Ten-Bit Interface (TBI) mode
Internally implements IEEE 802.3 MII management interface for monitoring and control of the internal PHY
Offers an external link interface: TBI as specified in IEEE 802.3z standard for 1000 Mb/s full duplex operation with 1.25 Gb/s SERDES
Receive and transmit IP and TCP/UDP checksum offloading capabilities
Automatic MDI crossover operation for 100BASE-TX and 10BASE-T modes
IEEE 802.1q VLAN support
Implements enhanced ACPI register set and power down functionality supporting D0 and D3 states, Wake on LAN capability with Power Management Event supportSpecifications
| Symbol |
Parameter |
Min |
Max |
Units |
| VDD(3.3) |
DC supply voltage on VDDD or AVDDH with
respect to VSS |
VSS - 0.5 |
4.6 |
V |
| VDD(2.5) |
DC supply voltage on AVDDL with respect to
VSS |
VSS - 0.5 |
4.6 or
VDD(2.5) + 0.5
(whichever is
less)b |
V |
| VDD(1.8) |
DC supply voltage on DVDDH with respect to
VSS |
VSS - 0.5 |
4.6 or
VDD(2.5) + 0.5
(whichever is
less)b |
V |
| VDD(1.5) |
DC supply voltage on DVDDL with respect to
VSS |
VSS - 0.5 |
.6 or
VDD(2.5) + 0.5
(whichever is
less)b |
V |
| VDD |
DC supply voltage |
VSS - 0.5 |
4.6 |
V |
| VI VO |
LVTTL input voltage |
VSS - 0.5 |
4.6 |
V |
| VI / VO |
5 V compatible input voltage |
VSS - 0.5 |
6.6 |
V |
| IO |
DC output current (by cell type):
IOL = 1mA
IOL = 2 mA
IOL = 3 mA
IOL = 6 mA
IOL = 9 mA
IOL = 12 mA
IOL = 18 mA
IOL = 24 mA |
|
3
7
10
20
30
40
60
75 |
mA |
| TSTG |
Storage temperature range |
-40 |
125 |
|
| |
ESD per MIL_STD-883 Test Method 3015,
Specification 2001V Latchup Over/Undershoot:
±150 mA, 125 C |
|
VDD
overstress:
VDD(3.3)(7.2 V) |
V |
a. Permanent device damage is likely to occur if the ratings in this table are exceeded. These values should not be used as the limits for normal device operations.
b. This specification applies to biasing the device to a steady state for an indefinite duration. During normal device owerup, explicit power sequencing is not required.
DescriptionThe 82544EI Gigabit Ethernet Controller is an integrated third-generation Ethernet LAN component capable of providing 1000, 100, and 10 Mbps data rates. 82544EI is a single-chip device, containing both the MAC and PHY layer functions, and optimized for LAN on Motherboard (LOM) designs, enterprise networking, and Internet appliances that use the Peripheral Component Interconnect (PCI) and PCI-X bus backplanes.
The 82544EI utilizes a 32/64 bit, 33/66 MHz direct interface to the PCI bus, compliant with the PCI Local Bus Specification, Revision 2.2. 82544EI also supports the emerging PCI-X extension to the PCI Local Bus, Revision 1.0a. The controller interfaces with the host processor through on-chip command and status registers and a shared host memory area, which is set up during initialization.
The 82544EI Gigabit Ethernet Controller provides a highly optimized architecture to deliver high performance and PCI/PCI-X bus efficiency. Its hardware, acceleration features enable offloading of various tasks, such as TCP/UDP/ IP checksum calculations and TCP segmentation, from the host processor. The 82544EI device accommodates highly-configurable Ethernet designs, which require minimal CPU overhead from interrupts and register accesses.
The physical layer circuitry provides an IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX and 10BASE-T applications. With the addition of an appropriate serializer/ deserializer (SERDES), the 82544EI controller also provides an Ethernet interface for 1000BASESX or 1000BASE-LX applications.
The 82544EI Gigabit Ethernet Controller is packaged in a 27 mm x 27 mm, 416-ball grid array.
82544EI Data Sheet
