81006AKLF

Specifications

Temperature C Voltage 3.3 V Package VFQFPN 20 Speed NA Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade


Description

6 CMOS OUT VCXO
ICS810001-21's Features

• Accepts various HD and SD references including hsync, transport and pixel clock rates
• Outputs HD and SD pixel rates
• One LVCMOS/LVTTL PLL clock output
• Two selectable LVCMOS/LVTTL input clocksLVCMOS input select lines
• VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking
• FemtoClock frequency multiplier provides low jitter, high frequency output
• FemtoClock range: 560MHz - 700MHz
• RMS phase jitter @148.3516484MHz, using a 26.973027MHz crystal (12kHz - 20MHz): 0.81ps (typical)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature

Description
The ICS810001-21 is a member of the HiperClockS? family of high performance clock solutions from ICS. The ICS810001-21 is a PLL based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. The ICS810001-21 contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation, and to support the complex PLL multiplication ratios needed for video rate conversion. The second stage is a FemtoClock frequency multiplier that provides the low jitter, high frequency video output clock.

Preset multiplication ratios are selected from internal lookup tables using ICS810001-21 input selection pins. The multiplication ratios are optimized to support most common video rates used in professional video system applications. The VCXO ICS810001-21 requires the use of an external, inexpensive pullable crystal. Two crystal connections are provided (pin selectable) so that both 60 and 59.94 base frame rates can be supported. The VCXO ICS810001-21 requires external passive loop filter components which are used to set the PLL loop bandwidth and damping characteristics.