80C187

Features:

High Performance 80-Bit Internal Architecture
Implements ANSIIEEE Standard 754- 1985 for Binary Floating-Point Arithmetic
Upward Object-Code Compatible from 8087
Fully Compatible with 387DX and 387S Math Coprocessors Implements all 387 Architectural Enhancements over 8087
Directly Interfaces with 80C186 CPU
80C18680C187 Provide a Software Binary Compatible Upgrade from 80186821888087 Systems
Expands 80C186's Data Types to Include 32- 64- 80-Bit Floating-Point 32- 64-Bit Integers and 18-Digit BCD Operands
Directly Extends 80C186's Instruction Set to Trigonometric Logarithmic Exponential and Arithmetic Instructions for All Data Types
Full-Range Transcendental Operationsfor SINE COSINE TANGENT ARCTANGENT and LOGARITHM
Built-In Exception Handling
Eight 80-Bit Numeric Registers Usable as Individually Addressable General Registers or as a Register Stack
Available in 40-Pin CERDIP and 44-Pin PLCC Package


Pinout




Specifications

Case TemperatureUnder Bias (T_C)................0to 85
Storage Temperature............................... 65to 150
Voltage on Any Pin
     with RespecttoGround ....................0.5V toV_CC 0.5V
Power Dissipation.................................................1.5W
NOTICE This is a production data sheet The specifi-cations are subject to change without notice
WARNING Stressing the device beyond the ''Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ''Operating Conditions'' is not recommended and ex- tended exposure beyond the ''Operating Conditions''may affect device reliability


Description

The Intel 80C187 is a high-performance math coprocessor that extends the architecture of the 80C186 with floating-point extended integer and BCD data types A computing system that includes the 80C187 fully conforms to the IEEE Floating-Point Standard The 80C187 adds over seventy mnemonics to the instruction set of the 80C186 including support for arithmetic logarithmic exponential and trigonometric mathematical operations The 80C187 is implemented with 15 micron high-speed CHMOS III technology and packaged in both a 40-pin CERDIP and a 44-pin PLCC package The 80C187 is upward object-code compatible from the 8087 math coprocessor and will execute code written for the 80387DX and 80387SX math coprocessors