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80960JA

Features: Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture -One Instruction/Clock Execution -Core Clock Rate is: 80960JA/JF 1x the Bus Clock 80960JD 2x the Bus Clock 80960JT 3x the Bus Clock -Load/Store Programming Model -Sixteen 32-Bit Global Registers -Sixt...

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SeekIC No. : 004253651 Detail

80960JA: Features: Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture -One Instruction/Clock Execution -Core Clock Rate is: 80960JA/JF 1x the Bus Clock 80960JD 2x the Bus ...

80960JA Data Sheet

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Part Number:
80960JA
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

Pin/Code Compatible with all 80960Jx Processors
High-Performance Embedded Architecture
   -One Instruction/Clock Execution
   -Core Clock Rate is:
      80960JA/JF 1x the Bus Clock
      80960JD 2x the Bus Clock
      80960JT 3x the Bus Clock
   -Load/Store Programming Model
   -Sixteen 32-Bit Global Registers
   -Sixteen 32-Bit Local Registers (8 sets)
   -Nine Addressing Modes
   -User/Supervisor Protection Model
Two-Way Set Associative Instruction Cache
   -80960JA - 2Kbyte
   -80960JF/JD - 4 Kbyte
   -80960JT - 16Kbyte
   -Programmable Cache-Locking Mechanism
Direct Mapped Data Cache
   -80960JA - 1Kbyte
   -80960JF/JD - 2 Kbyte
   -80960JT - 4 Kbyte
   -Write Through Operation
On-Chip Stack Frame Cache
   -Seven Register Sets Can Be Saved
   -Automatic Allocation on Call/Return
   -0-7 Frames Reserved for High-Priority Interrupts
On-Chip Data RAM
   -1 Kbyte Critical Variable Storage
   -Single-Cycle Access 3.3V Supply Voltage
   -5 V Tolerant Inputs
   -TTL Compatible Outputs
High Bandwidth Burst Bus
   -32-Bit Multiplexed Address/Data
   -Programmable Memory Configuration
   -Selectable 8-, 16-, 32-Bit Bus Widths
   -Supports Unaligned Accesses
   -Big or Little Endian Byte Ordering
High-Speed Interrupt Controller
   -31 Programmable Priorities
   -Eight Maskable Pins plus NMI
   -Up to 240 Vectors in Expanded Mode
Two On-Chip Timers
   -Independent 32-Bit Counting
   -Clock Prescaling by 1, 2, 4 or 8
   -lnternal Interrupt Sources
Halt Mode for Low Power
IEEE 1149.1 (JTAG) Boundary Scan Compatibility
Packages
-132-Lead Pin Grid Array (PGA)
-132-Lead Plastic Quad Flat Pack (PQFP)
-196-Ball Mini Plastic Ball Grid Array (MPBGA)


Pinout

This section describes the pins for the 80960Jx in the 132-pin ceramic Pin Grid Array (PGA) package, 132-lead Plastic Quad Flatpack Package (PQFP) and 196-ball Mini Plastic Ball Grid Array (MPBGA).
Section 3.1.1, "Functional Pin Definitions", describes pin function; Section 3.1.2, "80960Jx 132-Lead PGA Pinout", Section 3.1.3, "80960Jx 132-Lead PQFP Pinout" and Section 3.1.4, "80960Jx 196-Ball MPBGA Pinout", define the signal and pin locations for the supported package types.
Connection Diagram Connection Diagram Connection Diagram Connection Diagram Connection Diagram Connection Diagram


Specifications

Storage Temperature ..............................65  to +150 
Case Temperature Under Bias ................65  to +110 
Supply Voltage wrt. VSS...........................0.5 V to + 4.6 V
Voltage on VCC5 wrt. V SS.......................0.5 V to + 6.5 V
Voltage on Other Pins wrt. VSS  ......0.5 V to VCC  + 0.5 V
Note: This document contains information on products in the sampling and initial production phases of development. It is valid for the devices indicated in the revision history. The specifications within this data sheet are subject to change without notice. Verify with your local Intel sales office that you have the latest data sheet before finalizing a design.
Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.



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