80960HT

32-Bit Parallel Architecture
-Load/StoreArchitecture
-Sixteen32-Bit Global Registers
-Sixteen32-Bit Local Registers
-1.28GbyteInternalBandwidth (80MHz)
-On-Chip Register Cache
Processor Core Clock
-80960HA is1xBus Clock
-80960HD is2xBus Clock
-80960HTis3xBusClock
Binary CompatiblewithOther 80960 Processors
IssueUp To 150MillionInstructionsper Second
High-Performance On-ChipStorage
-16Kbyte Four-WaySet-Associative InstructionCache
-8KbyteFour-WaySet-AssociativeData Cache
-2 Kbyte General Purpose RAM
-Separate 128-Bit Internal PathsFor Instructions/Data
3.3V Supply Voltage
-5 V Tolerant Inputs
-TTL CompatibleOutputs Guarded Memory Unit
-Provides MemoryProtection
-User/SupervisorRead/Write/Execute
32-Bit DemultiplexedBurst Bus
-Per-Byte ParityGeneration/Checking
-AddressPipeliningOption
-Fully Programmable Wait State Generator
-Supports8-,16-or32-Bit BusWidths
-160Mbyte/s External Bandwidth (40MHz) High-SpeedInterrupt Controller
-Up to240External Interrupts
-31Fully Programmable Priorities
-Separate, Non-maskable Interrupt Pin Dual On-Chip32-Bit Timers
-Auto ReloadCapabilityandOne-Shot
-CLKIN Prescaling,÷1,2, 4or8
-JTAG Support - IEEE 1149.1 Compliant

Thissection definesthe 80960Hx pins. Table 6presentsthe legendforinterpreting thepin descriptionsinTable 7. All pinsfloat whilethe processor isinthe ONCE mode, except TDO,whichcan be driven active accordingto normal JTAG specifications.