74VCXH16245

Features:

• Designed for Low Voltage Operation: VCC = 1.65−3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 2.5 ns max for 3.0 to 3.6 V
3.0 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
• Static Drive: ±24 mA Drive at 3.0 V
±18 mA Drive at 2.3 V
±6 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
• IOFF Specification Guarantees High Impedance When VCC = 0 V*
• Near Zero Static Supply Current in All Three Logic States (20 A)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
• Pb−Free Package is Available*


Pinout




Specifications

Symbol	Parameter	Value	Condition	Unit
VCC	DC Supply Voltage	−0.5 to +4.6		V
VI	DC Input Voltage	−0.5 VI +4.6		V
VO	DC Output Voltage	−0.5 VO +4.6	Output in 3−State	V
		−0.5 VO VCC + 0.5	Note 1.; Outputs Active	V
IIK	DC Input Diode Current	−50	VI < GND	mA
IOK	DC Output Diode Current	−50	VO < GND	mA
		+50	VO > VCC	mA
IO	DC Output Source/Sink Current	±50		mA
ICC	DC Supply Current Per Supply Pin	±100		mA
IGND	DC Ground Current Per Ground Pin	±100		mA
TSTG	Storage Temperature Range	−65 to +150		°C

Description

The 74VCXH16245 is an advanced performance, non−inverting 16−bit transceiver. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems.

When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be over−voltage tolerant to 3.6 V.

The 74VCXH16245 is designed with byte control. It can be operated as two separate octals, or with the controls tied together, as a 16−bit wide function. The Transmit/Receive (T/Rn) inputs determine the direction of data flow through the bi−directional transceiver. Transmit(active−HIGH) enables data from A ports to B ports; Receive (active−LOW) enables data from B to A ports. The Output Enable inputs (OEn), when HIGH, disable both A and B ports by placing them in a HIGH Z condition. The data inputs include active bushold circuitry, eliminating the need for external pull−up resistors to hold unused or floating inputs at a valid logic state.