74VCX16835

Supply Voltage (V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . -0.5V to +4.6V
DC Input Voltage (V_I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . -0.5V to +4.6V
Output Voltage (V_O)
Outputs 3-STATE . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
Outputs Active (Note 5) . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . -0.5V to V_CC + 0.5V
DC Input Diode Current (I_IK)
VI < 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA
DC Output Diode Current (I_OK)
VO < 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . .. . . . . . . . .-50 mA
VO > V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50 mA
DC Output Source/Sink Current (IOL/IOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
DC V_CC or Ground Current per . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .±100 mA
Supply Pin (I_CC or Ground)
Storage Temperature Range (Tstg) . . . . . . . . . . . . . . . . . . . . . . . .  . . .-65°C to +150°C

The 74VCX16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled.Data transfers from the Inputs (In) to Ouputs (On) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output
port is in a high impedance state.

The 74VCX16835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V.

The 74VCX16835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.