74V1G80

Features: `HIGH SPEED: fMAX = 180MHz (TYP.) at VCC = 5V` LOW POWER DISSIPATION: ICC = 1 A(MAX.) at TA=25` HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)` POWER DOWN PROTECTION ON INPUTS`SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V` BALANCED PROPAGATION DELAYS: tPLH tPHL` ...

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74V1G80 Picture
SeekIC No. : 004251728 Detail

74V1G80: Features: `HIGH SPEED: fMAX = 180MHz (TYP.) at VCC = 5V` LOW POWER DISSIPATION: ICC = 1 A(MAX.) at TA=25` HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)` POWER DOWN PROTECTION ON INPUTS`SYMMETRIC...

floor Price/Ceiling Price

Part Number:
74V1G80
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

`HIGH SPEED: fMAX = 180MHz (TYP.) at VCC = 5V
` LOW POWER DISSIPATION: ICC = 1 A(MAX.) at TA=25
` HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)
` POWER DOWN PROTECTION ON INPUTS
`SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V
` BALANCED PROPAGATION DELAYS: tPLH  tPHL
` OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V
` IMPROVED LATCH-UP IMMUNITY



Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VCC
Supply Voltage
0.5 to 7.0
V
VI
DC Input Voltage
0.5 to 7.0
V
VO
DC Output Voltage
0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
20
mA
IOK
DC Output Diode Current
±20
mA
IO
DC Output Current
±25
mA
ICC or IGND
DC VCC or Ground Current
±50
mA
Tstg
Storage Temperature
65 to 150
TL
Lead Temperature (10 sec)
260

AbsoluteMaximumRatingsarethose values beyond whichdamage to the device may occur. Functional operation
under these condition isnot implied.




Description

The 74V1G80 is an advanced high-speed CMOS SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH INVERTED OUTPUT fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. it is designed to operate from 2V to 5.5V, making this device ideal for portable applications.

This D-Type flip-flop is controlled by a clock input (CK). On the positive transition of the clock, the Q output will be set to the logic inverted state that was setup at the D input.

Following the hold time interval, data of the 74V1G80 at the D input can be changed without affecting the level at the output. Power down protection is provided on input and 0 to 7V can be accepted on input with no regard to the supply voltage. This device can be used to interface 5V to 3V.

It's available in the commercial temperature range. All inputs and output are equipped with protection circuits of the 74V1G80 against static discharge, giving them ESD immunity and transient excess voltage.




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