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74LVC1G57

Features: · Wide supply voltage range from 1.65 V to 5.5 V· 5 V tolerant input/output for interfacing with 5 V logic· High noise immunity· Complies with JEDEC standard: · JESD8-7 (1.65 V to 1.95 V) · JESD8-5 (2.3 V to 2.7 V) · JESD8B/JESD36 (2.7 V to 3.6 V).· ±24 mA output drive (VCC = 3.0 V)· ESD...

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SeekIC No. : 004251282 Detail

74LVC1G57: Features: · Wide supply voltage range from 1.65 V to 5.5 V· 5 V tolerant input/output for interfacing with 5 V logic· High noise immunity· Complies with JEDEC standard: · JESD8-7 (1.65 V to 1.95 V) ...

74LVC1G57 Data Sheet

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Part Number:
74LVC1G57
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Wide supply voltage range from 1.65 V to 5.5 V
· 5 V tolerant input/output for interfacing with 5 V logic
· High noise immunity
· Complies with JEDEC standard:
   · JESD8-7 (1.65 V to 1.95 V)
   · JESD8-5 (2.3 V to 2.7 V)
   · JESD8B/JESD36 (2.7 V to 3.6 V).
· ±24 mA output drive (VCC = 3.0 V)
· ESD protection:
   ·HBM EIA/JESD22-A114-B exceeds 2000 V
   ·MM EIA/JESD22-A115-A exceeds 200 V.
· CMOS low power consumption
·Latch-up performance exceeds 250 mA
· Direct interface with TTL levels
· Inputs accept voltages up to 5 V
· Multiple package options
·Specified from -40 °C to +85 °C and -40 °C to +125 °C.


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS
MIN
MAX
UNIT
VCC supply voltage   -0.5 +6.5
V
IIK input diode current VI < 0 V - -50
mA
VI input voltage                                     [1] -0.5 +6.5
V
IOK output diode current VO > VCC or VO < 0 V - ±50
mA
VO output voltage active mode              [1][2] -0.5 +6.5
V
Power-down mode   [1][2] -0.5 +6.5
V
IO output source or sink
current		 VO = 0 V to VCC - ±50
mA



Description

The 74LVC1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

The 74LVC1G57 is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND. All inputs (A, B and C) have Schmitt-trigger action. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.




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