Features: . 5V tolerant inputs and outputs. 2.3V - 3.6V VCC specifications provided. 7.0 ns tPD max (VCC= 3.3V), 10 A ICC m ax . Power down high impedance inputs and outputs. Supports live insertion/withdrawal (Note 1). ±24 mA output drive (VCC = 3.0V). Implements patented noise/EMI reduction cir...
74LCX646: Features: . 5V tolerant inputs and outputs. 2.3V - 3.6V VCC specifications provided. 7.0 ns tPD max (VCC= 3.3V), 10 A ICC m ax . Power down high impedance inputs and outputs. Supports live insertio...
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Gates (AND / NAND / OR / NOR) Quad 2-Input NAND Gate with 5V Tol Inp
. 5V tolerant inputs and outputs
. 2.3V - 3.6V VCC specifications provided
. 7.0 ns tPD max (V CC = 3.3V), 10 A I CC m ax
. Power down high impedance inputs and outputs
. Supports live insertion/withdrawal (Note 1)
. ±24 mA output drive (VCC = 3.0V)
. Implements patented noise/EMI reduction circuitry
. Latch-up performance exceeds 500 mA
. ESD performance:
Human body model > 2000V
Machine model > 200V
Symbol |
Parameter |
Value |
Conditions |
Units |
VCC |
Supply Voltage |
- 0.5 to +7.0 |
|
V |
VI |
DC Input Voltage |
-0.5 to +7.0 |
|
V |
|
DC Output Voltage |
-0.5 to +7.0 |
Output in 3-STATE |
V |
IIK |
DC Input Diode Current |
|
VI <GND |
mA |
IOK |
DC Output Diode Current |
-50 |
VO< GND |
mA |
IO |
DC Output Source/Sink Current |
|
|
mA |
ICC |
DC Supply Current per Supply Pin |
±100 |
|
mA |
IGND |
DC Ground Current per Ground Pin |
±100 |
|
mA |
TSTG |
Storage Temperature |
-65 to +150 |
|
|
The 74LCX646 consists of registered bus transceiver circuits,D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data of the 74LCX646 on the A or B bus will beloaded into the respective registers on the LOW-to-HIGH transition of the appropriate pin (CPAB or CPBA) (see Functional Description).
The 74LCX646 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment.
The 74LCX646 is fabricated with an advanced CMOS tech- nology to achieve high speed operation while maintaining CMOS low power dissipation.