Features: HIGH SPEED GTL/GTL+ UNIVERSAL
TRANSCEIVER:
tPD = 4.6 ns (MAX.) A to B at VCC = 3V
COMBINES D-TYPE LATCHES AND D-TYPE
FLIP-FLOPS FOR OPERATION IN
TRANSPARENT, LATCHED, OR CLOCKED
MODE
OPERATING VOLTAGE RANGE:
VCC(OPR) = 3.0V to 3.6V
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL=24mA (MIN) at VCC = 3V (A PORT)
OUTPUT IMPEDANCE:
IOL = 100mA (MIN) at VCC = 3V (B PORT)
HIGH-IMPEDANCE STATE DURING POWER
UP AND POWER DOWN up to
VCC=BIASVCC=1.5V PERMITT LIVE
INSERTION
B-PORT PRECHARGED BY BIASVCC
REDUCE NOISE ON THE LINE DURING
LIVE INSERTION
EDGE RATE-CONTROL INPUT
CONFIGURES THE B-PORT OUTPUT RISE
AND FALL TIMES
BUS HOLD ON DATA INPUTS ELIMINATES
THE NEED FOR EXTERNAL PULL-UP/
PULL-DOWN RESISTORS (A PORT)
DISTRIBUTED VCC AND GND PIN
CONFIGURATION MINIMIZES HIGH-SPEED
SWITCHING NOISE IN PARALLEL
COMUNICATIONS
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 1655
Pinout
Specifications
| Symbol |
Parameter |
Value |
Unit |
| VCC |
Supply Voltage, Bias VCC |
-0.5 to +4.6 |
V |
| VIA |
DC Input Voltage A Side, Control Input |
-0.5 to +4.6 |
V |
| VIB |
DC Input Voltage B Side, VERC, VREF |
-0.5 to +4.6 |
V |
| VOA |
DC Output Voltage A Side |
-0.5 to +4.6 |
V |
| VOB |
DC Output Voltage B Side |
-0.5 to +4.6 |
V |
| IIK |
DC Input Diode Current |
- 50 |
mA |
| IOK |
DC Output Diode Current |
- 50 |
mA |
| IOA |
DC Output Current A Side |
± 48 |
mA |
| IOB |
DC Output Current B Side in the Low State |
200 |
mA |
| Tstg |
Storage Temperature |
-65 to +150 |
|
| TL |
Lead Temperature (10 sec) |
300 |
|
Absolute Maximum Rating are those value beyond which damage to the device may occur. Functional operation under these condition is not implied
DescriptionThe 74GTL1655A devices are 16-bit high-drive 100mA), low-output-impedance universal bus low-output-impedance universal bus transceivers designed for backplane applications.
The 74GTL1655A devices provide live-insertion capability for backplane applications by tolerating active signals on the data ports when the devices are powered off. In addition, a biasing pin preconditions the GTL/GTL+ port to minimize disruption to an active backplane.
The edge rate-control (VERC) input of the 74GTL1655A is provided so the rise and fall time of the B outputs can be configured to optimize for various backplane loading conditions. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLK) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB of the 74GTL1655A is low, the A data is latched if CLK is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLK. The output enable (OE) is used to disable both ports simultaneously.
Active bus-hold circuitry of the 74GTL1655A is provided on the A port to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5V, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
All input and output of the 74GTL1655A are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
74GTL1655A Data Sheet
